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// dcr_env.svh: the DCRouter test environment (DCRouter step 4). Included inside `module tb`.
// Sources: queue_pkt() adds a packet to an input's queue; a driver per input sends its flits,
//   holding data steady while in_rdy is low, with gap_pct[i] percent idle cycles between flits.
//   Header = {dst, prio, len, src[1:0], seq[6:0]}; tail = {8'h00, CRC-8} (inverted when bad).
// Sinks: one 4-slot sink per output frees a slot with drain_pct[o] percent chance per cycle and
//   returns a credit for it; more than 4 flits in a sink is a credit overrun.
// Scoreboard: an accepted flit is expected at its packet's output, in order within its flow
//   (input, output); out_err is expected on the tail of a packet with a bad CRC or length 0.
// APB: apb_wr, apb_rd, check_reg. wait_drain() waits until every queued flit has arrived.
// End of test: finish(name) prints exactly one PASS or FAIL line.
logic clk = 0;
always #5 clk = ~clk;
logic rst = 1;
logic [3:0]  in_vld = 0, in_last = 0, in_rdy, out_vld, out_last, out_err, out_crd = 0;
logic [63:0] in_data = 0, out_data;
logic        psel = 0, penable = 0, pwrite = 0, pready, pslverr, sleeping;
logic [7:0]  paddr = 0;
logic [31:0] pwdata = 0, prdata;
dcrouter dut (.*);

int errors = 0;
function automatic void fail(string msg);
  if (errors < 5) $display("ERROR @%0t: %s", $time, msg);
  errors++;
endfunction

function automatic logic [7:0] crc8(input logic [7:0] c, input logic [15:0] d);
  logic [7:0] x;
  x = c;
  for (int k = 15; k >= 0; k--) x = (x[7] ^ d[k]) ? {x[6:0], 1'b0} ^ 8'h07 : {x[6:0], 1'b0};
  return x;
endfunction

// ---------------- sources ----------------
typedef struct packed { logic last, err; logic [1:0] dst; logic [15:0] data; } flit_t;
flit_t fq [4][$];               // flits waiting to be driven, per input
flit_t drv [4];                 // the flit on in_data now
int    gap_pct [4] = '{0, 0, 0, 0};
int    seq [4] = '{0, 0, 0, 0};
int    sent_pkts [4] = '{0, 0, 0, 0}, bad_pkts [4] = '{0, 0, 0, 0};

task automatic queue_pkt(int i, int dst, int prio, int len, bit bad_crc = 0);
  logic [15:0] f [$];
  logic [7:0]  c;
  f.push_back({2'(dst), 1'(prio), 4'(len), 2'(i), 7'(seq[i])});
  seq[i]++;
  for (int k = 1; k <= len; k++) f.push_back(16'($urandom));
  c = 8'h00;
  foreach (f[k]) c = crc8(c, f[k]);
  f.push_back({8'h00, bad_crc ? ~c : c});
  foreach (f[k]) fq[i].push_back({k == f.size() - 1, bad_crc || len == 0, 2'(dst), f[k]});
  sent_pkts[i]++;
  if (bad_crc || len == 0) bad_pkts[i]++;
endtask

logic [16:0] exp_q [4][4][$];   // expected {err on tail, data} per (input, output)
for (genvar i = 0; i < 4; i++) begin : g_src
  always @(posedge clk) if (!rst) begin
    if (in_vld[i] && in_rdy[i]) exp_q[i][drv[i].dst].push_back({drv[i].last && drv[i].err, drv[i].data});
    if (!(in_vld[i] && !in_rdy[i])) begin          // never change valid data while stalled
      in_vld[i] <= 0;
      if (fq[i].size() > 0 && $urandom_range(0, 99) >= gap_pct[i]) begin
        drv[i] = fq[i].pop_front();
        in_vld[i] <= 1;
        in_data[16*i +: 16] <= drv[i].data;
        in_last[i] <= drv[i].last;
      end
    end
  end
end

// ---------------- sinks and scoreboard ----------------
int drain_pct [4] = '{100, 100, 100, 100};
int occ [4] = '{0, 0, 0, 0}, got_pkts [4] = '{0, 0, 0, 0}, got_flits [4] = '{0, 0, 0, 0};
int cur_src [4];
bit in_pkt [4] = '{0, 0, 0, 0};
for (genvar o = 0; o < 4; o++) begin : g_snk
  always @(posedge clk) begin
    int n;
    out_crd[o] <= 0;
    n = occ[o];
    if (!rst && out_vld[o]) begin
      logic [15:0] d;
      logic [16:0] e;
      d = out_data[16*o +: 16];
      n++; got_flits[o]++;
      if (!in_pkt[o]) begin cur_src[o] = int'(d[8:7]); in_pkt[o] = 1; end
      if (exp_q[cur_src[o]][o].size() == 0) fail($sformatf("out%0d: unexpected flit %h", o, d));
      else begin
        e = exp_q[cur_src[o]][o].pop_front();
        if (e[15:0] !== d) fail($sformatf("out%0d: flit %h, expected %h from input %0d", o, d, e[15:0], cur_src[o]));
        if (out_err[o] !== (out_last[o] && e[16])) fail($sformatf("out%0d: out_err %0b on flit %h, expected %0b", o, out_err[o], d, out_last[o] && e[16]));
      end
      if (out_last[o]) begin in_pkt[o] = 0; got_pkts[o]++; end
    end
    if (n > 4) fail($sformatf("out%0d: %0d flits in a 4-slot sink (credit overrun)", o, n));
    if (n > 0 && $urandom_range(0, 99) < drain_pct[o]) begin n--; out_crd[o] <= 1; end
    occ[o] = n;
  end
end

function automatic int pending();
  int n;
  n = 0;
  for (int i = 0; i < 4; i++) begin
    n += fq[i].size() + (in_vld[i] ? 1 : 0);
    for (int o = 0; o < 4; o++) n += exp_q[i][o].size();
  end
  return n;
endfunction

task automatic wait_drain(int max_cycles = 5000);
  int c;
  c = 0;
  while (pending() > 0 && c < max_cycles) begin @(posedge clk); c++; end
  if (pending() > 0) fail($sformatf("%0d flits still pending after %0d cycles (lost or stuck)", pending(), max_cycles));
  repeat (4) @(posedge clk);
endtask

// ---------------- APB ----------------
logic [31:0] rd;
logic        rd_err;
task automatic apb(input bit wr, input logic [7:0] a, input logic [31:0] wd);
  @(posedge clk); psel <= 1; penable <= 0; pwrite <= wr; paddr <= a; pwdata <= wd;
  @(posedge clk); penable <= 1;
  @(posedge clk); rd = prdata; rd_err = pslverr; psel <= 0; penable <= 0; pwrite <= 0;
endtask
task automatic apb_wr(input logic [7:0] a, input logic [31:0] wd); apb(1, a, wd); endtask
task automatic apb_rd(input logic [7:0] a); apb(0, a, 0); endtask
task automatic check_reg(input logic [7:0] a, input logic [31:0] expv, input string what);
  apb_rd(a);
  if (rd !== expv) fail($sformatf("%s: read %0h, expected %0h", what, rd, expv));
endtask

task automatic reset_dut();
  rst <= 1;
  repeat (3) @(posedge clk);
  rst <= 0;
endtask

task automatic finish(string name);
  if (errors == 0) $display("PASS: %s", name);
  else $display("FAIL: %s, %0d errors", name, errors);
  $finish;
endtask
initial begin #5000000; $display("FAIL: global timeout"); $finish; end

`ifdef WAVE
initial begin $dumpfile("wave.vcd"); $dumpvars(0, tb); end
wire        in0_vld = in_vld[0], in0_rdy = in_rdy[0], in0_last = in_last[0];
wire [15:0] in0_data = in_data[15:0];
wire        out1_vld = out_vld[1], out1_last = out_last[1], out1_err = out_err[1], out1_crd = out_crd[1];
wire [15:0] out1_data = out_data[31:16];
`endif

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// uses: dcrouter
// DCRouter step 4: directed tests, one per heading of the specification. Each test drives
// one known case and checks its rule; the environment's scoreboard checks every flit.
module tb;
  `include "dcr_env.svh"
  int n0;
  initial begin
    reset_dut();
    // D1 reset values (R11)
    check_reg(8'h00, 32'h3F, "CTRL after reset");
    // D2 one packet from every input to the next output (R3)
    for (int i = 0; i < 4; i++) queue_pkt(i, (i + 1) % 4, 0, 2);
    wait_drain();
    // D3 the shortest and the longest packet (R4)
    queue_pkt(0, 1, 0, 1);
    queue_pkt(0, 1, 0, 15);
    wait_drain();
    // D4 a length-0 header is flagged and counted (R5)
    queue_pkt(0, 2, 0, 0);
    wait_drain();
    check_reg(8'h10, 1, "ERR_CNT0 after a length-0 packet");
    // D5 a bad CRC is flagged and counted (R8, R9)
    queue_pkt(1, 0, 0, 3, 1);
    wait_drain();
    check_reg(8'h14, 1, "ERR_CNT1 after a bad CRC");
    // D6 credits: with output 3's sink full, exactly 4 flits leave (R7)
    drain_pct[3] = 0;
    n0 = got_flits[3];
    queue_pkt(0, 3, 0, 8);
    repeat (40) @(posedge clk);
    if (got_flits[3] - n0 != 4) fail($sformatf("%0d flits left output 3 with no credits returned, expected 4", got_flits[3] - n0));
    drain_pct[3] = 100;
    wait_drain();
    // D7 counters: ERR_CNT0 clears; PKT_CNT matches the packets seen (R9, R10)
    apb_wr(8'h10, 0);
    check_reg(8'h10, 0, "ERR_CNT0 after a clear");
    for (int k = 0; k < 4; k++) check_reg(8'h20 + 8'(4 * k), got_pkts[k], $sformatf("PKT_CNT%0d", k));
    // D8 an unmapped address answers pslverr (R12)
    apb_rd(8'h40);
    if (rd_err !== 1'b1) fail("no pslverr for unmapped address 0x40");
    // D9 sleep after idle, then wake with a packet (R13)
    repeat (20) @(posedge clk);
    if (!sleeping) fail("not sleeping after 20 idle cycles");
    queue_pkt(0, 1, 0, 2);
    wait_drain();
    finish("directed tests D1-D9 all passed");
  end
endmodule