Answer each question out loud before opening it. If you miss more than three in the checkpoint, revisit the lessons linked at the end.
Bring-up, specific deep states, register and reset checks, corners random will not reach, and a permanent test for every fixed bug; each is a single point in a feature's space.
Its choices do not share the writer's blind spots, and every random transaction exercises timing and combinations for free.
To keep it inside the legal space; constraints model the environment, with explicit modes for deliberate errors.
Shape the distribution: keep most weight broad and put extra weight on boundary values, since corners multiply their probabilities.
About a million trials on average, and about three million for 95% confidence.
Inject every fault type deliberately, crossed with modes, check every response and side effect, drive the limits and check recovery.
Random timing: source gaps, sink stalls, changing profiles and independent settings per port, with an audit of hidden state at the end.
Reproduce the seed on the same build, debug it, keep the seed and a directed test, and add bias or coverage for the rare trigger.
Task. You inherit a random regression for a cache controller: uniform random addresses over 4 GB, reads and writes 50/50, no idle cycles, a memory model that always answers in 2 cycles, one fixed seed per test. List what this stimulus will rarely or never exercise, and how you would change it.
Rarely or never: hits (uniform addresses over 4 GB almost never reuse a line, so the cache misses constantly), conflicts on one set and evictions of dirty lines, read-after-write to the same line, back-pressure and slow or out-of-order memory responses, idle periods (power or clock gating), error responses from memory, and anything that varies by seed. Changes: constrain addresses to a small working set with a mixture (most traffic in a few sets, some uniform) to create hits, conflicts and evictions; flows of accesses to the same line; a memory model with random latency, stalls and error injection; random idle gaps; layered scenarios such as fill, thrash, flush; fresh seeds nightly with many seeds per test; and coverage on hit, miss, eviction and conflict to see what was reached.
10 of 24.
Its one bad-CRC packet was low priority; the bug only affects high-priority packets.
About 695 (n·H_n).
:= gives the weight to every value of a range; :/ shares it across the range.
24.
The traffic pattern layer: a hot spot of mixed-priority inputs on one output.
BUG_13, BUG_14, BUG_15 and BUG_19.
BUG_20 and BUG_22.
16.
BUG_5, 6, 7 (reached but no fairness or priority check) and BUG_16, 23 (never reached: no packet-counter clear, no disabled port).