Bottleneck Analysis Framework — Silicon & PPA Impact

Silicon, power, area, and timing impact

PMU and trace infrastructure have direct silicon area and power implications.

Area drivers

• Buffers/tables/SRAM

• Bypass and issue width wiring

• Coherency metadata

Power drivers

• Activity factor

• SRAM energy

• Wake-up bursts

Timing and frequency impact

• Critical path movement

• Macro distance

• Frequency pressure

PD and floorplan consequences

• Place hot structures near consumers

• Macro placement constraints

• NoC congestion

Verification burden

• More states/policies

• Ordering regressions

• Traceable workload proof

PPA — Bottleneck Analysis Framework
area/power/timing/verif all workload-dependent

Key takeaways

• No architecture signoff without PPA statement

• PD latency budget can force architecture change

Architecture deep dive

PMU evidence beats intuition for architecture decisions.

Concept diagram

TOP-DOWN PERFORMANCE METHOD

Total cycles
 ├─ Retiring useful work
 ├─ Frontend bound
 ├─ Bad speculation
 ├─ Backend core bound
 └─ Backend memory bound

Only after classification should you propose cache, branch, pipeline, or NoC changes.

Metric graph

ROOFLINE SKETCH

Performance
  ^
  |                     compute roof
  |-------------------------------
  |                   /
  |                 /
  |               /   ● workload A (compute-bound)
  |             /
  |   ● workload B (memory-bound)
  +---------------------------------> arithmetic intensity
        memory bandwidth slope

Metrics and artifacts

• PMU event sets

• roofline chart

• top-down stall breakdown

• workload sensitivity matrix

Mini case study

Team proposed wider SIMD but roofline showed memory-bound kernel — bandwidth upgrade and locality fix delivered 2× speedup at lower area cost.

Debug branches

• If counters disagree with sim, align workload and warmup.

• If bottleneck unclear, use top-down method before microarch tweaks.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

• Connect every architecture claim to a workload and measurable metric.

• State verification and PPA impact before proposing design changes.

Common pitfalls

• Feature-driven design without MPKI/IPC/bandwidth evidence.

• Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.