Bottleneck Analysis Framework — Software / Programmer View

Software and programmer view

Profiling culture must align with hardware counters or teams optimize the wrong layer.

What programmers feel

• Tail latency under contention

• Layout-sensitive cliffs

• Rare ordering bugs

API / ABI / runtime implications

• Alignment/allocation

• Pinning/domain awareness

• Fence semantics

Compiler and runtime interaction

• Prefetch sensitivity

• Padding/layout

• Allocator behavior

Software-side mitigations

• Improve locality

• Reduce false sharing

• Expose counters

SOFTWARE — Bottleneck Analysis Framework
per-core counters beat shared hot counters for coherence traffic

Architecture deep dive

PMU evidence beats intuition for architecture decisions.

Concept diagram

TOP-DOWN PERFORMANCE METHOD

Total cycles
 ├─ Retiring useful work
 ├─ Frontend bound
 ├─ Bad speculation
 ├─ Backend core bound
 └─ Backend memory bound

Only after classification should you propose cache, branch, pipeline, or NoC changes.

Metric graph

ROOFLINE SKETCH

Performance
  ^
  |                     compute roof
  |-------------------------------
  |                   /
  |                 /
  |               /   ● workload A (compute-bound)
  |             /
  |   ● workload B (memory-bound)
  +---------------------------------> arithmetic intensity
        memory bandwidth slope

Metrics and artifacts

• PMU event sets

• roofline chart

• top-down stall breakdown

• workload sensitivity matrix

Mini case study

Team proposed wider SIMD but roofline showed memory-bound kernel — bandwidth upgrade and locality fix delivered 2× speedup at lower area cost.

Debug branches

• If counters disagree with sim, align workload and warmup.

• If bottleneck unclear, use top-down method before microarch tweaks.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

• Connect every architecture claim to a workload and measurable metric.

• State verification and PPA impact before proposing design changes.

Common pitfalls

• Feature-driven design without MPKI/IPC/bandwidth evidence.

• Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.