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Roofline Thinking for SoC Tradeoffs — Review Checklist
Review Checklist for Roofline Thinking for SoC Tradeoffs (Performance Analysis).
Review gate
Inputs versioned and match workload/model/RTL tag
Primary metric meets target or documented product tradeoff
Regression workloads executed on tagged model
Risks logged with owner and date
Handoff notes updated for next stage
Smoke check (5 minutes)
Every checklist item has an owner
Failed items have owner, mitigation, and decision record
Definition of done for a senior owner
The exact workload, model/RTL tag, counter setup, and analysis window are recorded.
The primary metric is clean, improved, or accepted as a documented product tradeoff: Workload roofline placement report.
The change is explained by mechanism, not by architecture folklore.
Regression coverage includes the obvious downstream domains: Area-power-performance budgeting and accelerator roadmap choices..
Residual risk has an owner, approval path, and expiration date.
The lesson is captured as a methodology guardrail if it can recur.
Smoke check (5 minutes)
Could another engineer reproduce the conclusion from the notes alone?
Would you sign this off if the design came from another team?
Review visual
TRADEOFF MATRIX — Roofline Thinking for SoC Tradeoffs
+----------------------+----------------------+----------------------+----------------------+
| Option | Helps | Can hurt | Validation needed |
+----------------------+----------------------+----------------------+----------------------+
| Larger / wider block | peak perf, miss rate | area, power, timing | workload sweep |
| Smarter policy | hit rate, QoS, IPC | verification risk | corner cases + PMU |
| More buffering | latency tails, stalls| deadlock, leakage | stress traffic tests |
| Software contract | locality, ordering | portability, APIs | production workload |
+----------------------+----------------------+----------------------+----------------------+
Senior rule: pick the smallest change that proves or disproves the mechanism.Architecture deep dive
PMU evidence beats intuition for architecture decisions.
Concept diagram
TOP-DOWN PERFORMANCE METHOD
Total cycles
├─ Retiring useful work
├─ Frontend bound
├─ Bad speculation
├─ Backend core bound
└─ Backend memory bound
Only after classification should you propose cache, branch, pipeline, or NoC changes.Metric graph
ROOFLINE SKETCH
Performance
^
| compute roof
|-------------------------------
| /
| /
| / ● workload A (compute-bound)
| /
| ● workload B (memory-bound)
+---------------------------------> arithmetic intensity
memory bandwidth slopeMetrics and artifacts
PMU event sets
roofline chart
top-down stall breakdown
workload sensitivity matrix
Mini case study
Team proposed wider SIMD but roofline showed memory-bound kernel — bandwidth upgrade and locality fix delivered 2× speedup at lower area cost.
Debug branches
If counters disagree with sim, align workload and warmup.
If bottleneck unclear, use top-down method before microarch tweaks.
Senior review question
Ask: what single metric would prove this concept is working or failing on your workload?
Key takeaways
Connect every architecture claim to a workload and measurable metric.
State verification and PPA impact before proposing design changes.
Common pitfalls
Feature-driven design without MPKI/IPC/bandwidth evidence.
Ignoring coherency and NoC traffic in cache and accelerator sizing.
Study notes
Re-read this topic with one concrete workload.