Roofline Thinking for SoC Tradeoffs — Design Space Exploration

Design space exploration

For Roofline Thinking for SoC Tradeoffs, senior architects do not pick one answer — they map the design space, estimate metric movement, and choose based on product constraints.

Option A — conservative

• Conservative: helps lower risk

• Risk: less upside

• Validate with: baseline suite

Option B — balanced

• Balanced: helps good perf/watt

• Risk: may miss peak

• Validate with: multi-workload sweep

Option C — aggressive

• Aggressive: helps peak wins

• Risk: PPA/DV risk

• Validate with: stress suite

Option D — software-first

• Software-first: helps low silicon

• Risk: fragile

• Validate with: controlled apps

DESIGN SPACE — Roofline Thinking for SoC Tradeoffs
low risk -> balanced -> aggressive
with software-first as alternate axis

Common pitfalls

• Aggressive hardware before workload proof

• Balanced by habit without numbers

Architecture deep dive

PMU evidence beats intuition for architecture decisions.

Concept diagram

TOP-DOWN PERFORMANCE METHOD

Total cycles
 ├─ Retiring useful work
 ├─ Frontend bound
 ├─ Bad speculation
 ├─ Backend core bound
 └─ Backend memory bound

Only after classification should you propose cache, branch, pipeline, or NoC changes.

Metric graph

ROOFLINE SKETCH

Performance
  ^
  |                     compute roof
  |-------------------------------
  |                   /
  |                 /
  |               /   ● workload A (compute-bound)
  |             /
  |   ● workload B (memory-bound)
  +---------------------------------> arithmetic intensity
        memory bandwidth slope

Metrics and artifacts

• PMU event sets

• roofline chart

• top-down stall breakdown

• workload sensitivity matrix

Mini case study

Team proposed wider SIMD but roofline showed memory-bound kernel — bandwidth upgrade and locality fix delivered 2× speedup at lower area cost.

Debug branches

• If counters disagree with sim, align workload and warmup.

• If bottleneck unclear, use top-down method before microarch tweaks.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

• Connect every architecture claim to a workload and measurable metric.

• State verification and PPA impact before proposing design changes.

Common pitfalls

• Feature-driven design without MPKI/IPC/bandwidth evidence.

• Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.