Pulse Synchronizers: Worked Example

Worked example

Worked Example for Pulse Synchronizers focuses on pulse miss rate, minimum pulse width margin, duplication events. The goal is to convert issue observations into mechanism-backed closure decisions.

A milestone review shows pulse miss rate, minimum pulse width margin, duplication events. Teams disagree on severity. The right move is to isolate one representative issue, prove mechanism class, and decide fix or waiver with explicit residual risk.

Crossing under inspection

CROSSING FLOW — Pulse Synchronizers

source clock domain -> launch signal -> crossing structure -> destination sample
      |                    |                 |                    |
   source FF           protocol           sync / fifo         destination FF

Key metric: pulse miss rate, minimum pulse width margin, duplication events

Pulse-safe transfer

short pulse in src domain
   -> toggle bit
   -> sync toggle into dest
   -> edge detect in dest

Avoid pulse loss when destination clock is slower.

1. Capture warning, waveform, and owning module context.

2. Tag mode/reset/traffic state for the failure.

3. Validate assumptions against spec and assertions.

4. Compare outcome with pulse width assumptions, toggle synchronizer checks, simulation traces.

5. Choose one reversible action and define regression upfront.

Did the action work?

BEFORE / AFTER — Pulse Synchronizers

open critical issues
  ^
  |  o baseline
  |     o after fix batch
  |         o after protocol proof
  |             o signoff-ready
  +---------------------------------> closure iteration

Track issue burn-down with evidence quality, not only count.

CDC/RDC deep dive

Protocol correctness is the bridge between structural clean and functional safe.

Concept diagram

PROTOCOL FLOW

intent -> transport protocol -> synchronization -> destination acceptance

Metric graph

PROTOCOL ISSUE BURNDOWN

open issues: 20 -> 11 -> 5 -> 0

Reports and artifacts

• FIFO pointer proofs

• req/ack liveness

• pulse miss checks

• protocol assertions

Mini case study

Async FIFO empty/full logic looked correct until gray decode mismatch appeared during reset overlap.

Debug branches

• Pointer sync audit

• formal liveness checks

• reset interaction review

Senior review question

Ask: what evidence proves this risk is closed for silicon, not just tool-clean?

Key takeaways

• State crossing class, assumptions, and owner with every issue.

• Run structural and dynamic regressions after each fix.

Common pitfalls

• Treating all warnings as equivalent risk.

• Waiving issues without containment evidence.

• Skipping reset and reconvergence stress after CDC fixes.

Principal CDC/RDC review addendum

Pulse crossings require width expansion, toggle encoding, or ack-backed transport because short pulses can vanish between destination sampling edges.

Metric: pulse miss rate, minimum pulse width margin, duplication events