The symptom is data nobody sent: a control register reads a value the source never wrote, or a state machine takes a transition its inputs cannot explain, once in thousands of runs. In a waveform the signature is a destination word that matches neither the old nor the new source value for exactly the synchroniser latency, then settles to the new value. In a log it is a single impossible sample surrounded by correct ones.
The tearing mechanism itself is taught in the bus-tearing lesson of the metastability section, with its own simulated waveform: bits of one word arriving through independent synchronisers mix old and new values whenever several bits change together. This lesson adds only the debug angle, so read that lesson first and return here with the picture in mind.
Observation | Points to tearing when | Points elsewhere when |
|---|---|---|
An impossible intermediate value | It lasts exactly the synchroniser depth, then corrects itself. | It persists: that is a logic bug, not a crossing. |
Which transitions tear | Single-bit steps are free of tearing (the settling rules still apply); multi-bit steps tear. | Single-bit steps corrupt too: suspect the synchroniser structure itself. |
Failure rate versus traffic | Rises with transition rate on the bus. | Constant per boot regardless of traffic: suspect reset or initialisation. |
Structural analysis reports the multi-bit bus crossing without a protocol, the same class the violation-classes lesson lists. The debug question for the report is always whether the finding was absent or was waived: absent means a setup hole such as a missing clock, while waived as quasi-static without qualification evidence means the waiver process failed, not the analysis.
Fix it with the pattern that fits the value type: Gray code for stepping counters, a handshake or load pulse for arbitrary words, a FIFO for streams. The guard is structural first and directed second: a standing check that no multi-bit bus crosses without a recognised protocol, plus a directed test that steps the bus through its worst multi-bit transitions, such as 0111 to 1000, with skew in the model. A thousand random crossings prove nothing; the all-bits-change transition is the one that tears.
Tearing: the duration matches the synchroniser depth and it self-corrects. A logic bug would persist or repeat deterministically.
Either the analysis never saw the crossing because of a setup hole, or it flagged it and the finding was waived without evidence. Check the setup and the waiver log in that order.