Thirty seconds per question, one line per answer, no hedging. If an answer needs two lines, you do not know it yet: follow its link, re-learn the lesson, and return. Score 16 out of 20 strong before the interview.
# | Question | Strong one-line answer |
|---|---|---|
1 | Define a crossing. | Launch flop on one clock net, capture flop on another; nets decide, never frequencies. |
2 | Same frequency, two oscillators: crossing? | Yes: independent sources drift through every phase, so every path between them crosses. |
3 | What is metastability in ten words? | Late-resolving capture flop feeding divergent values downstream. |
4 | What does the second flop buy? | A full destination period of settling time; margin, not certainty. |
5 | Logic between synchroniser flops? | Defect, always: it voids the settling argument and diverges fanout. |
6 | Lost versus duplicated event? | Fast pulse missed by a slow clock versus slow level counted twice by a fast one. |
7 | Torn bus in one line? | Multi-bit change sampled mid-flight across per-bit synchronisers: old and new mixed. |
8 | When is two-flop capture enough? | Single-bit level held stable for more than two destination periods (measured against the slowest destination period in any supported mode), nothing else. |
9 | Pulse into a slower clock: scheme? | Toggle synchroniser with a spacing rule, or handshake if spacing is unguaranteed. |
10 | Toggle contract in one line? | Spaced events, known reset values, one destination strobe per toggle, proven. |
11 | Two-phase versus four-phase? | Transition-signalled throughput versus return-to-idle simplicity; both owe liveness. |
12 | Gray rule in one line? | One bit per step so samples resolve old-or-new; breaks on multi-step jumps. |
13 | Where are full and empty made? | Empty in the read domain, full in the write domain, each from one local plus one synchronised pointer. |
14 | Reconvergence in one line? | Two separately synchronised paths rejoining in one gate, where skew glitches the output. |
15 | Why is deassertion the reset hazard? | Release races the clock (recovery/removal); assertion races nothing. |
16 | One net, two release cycles: how many reset domains? | Two: release behaviour defines the domain, not the net name. |
17 | What does simulation prove about CDC? | Protocol behaviour under traffic; never safety, never rates. |
18 | What does formal add? | Proof over all alignments and sequences for the modelled protocol. |
19 | Classic constraint mistake? | Blanket false paths that silence real paths; group clocks, bound delays, review exceptions. |
20 | What does a waiver need? | Five fields: the finding reference, a written protocol argument, assertion or simulation proof, a constraint reference, and an owner with an expiry condition. |
17, 18, 19, and 20: methods and process. If those are your weak four, re-read the signoff methodology section before more circuit revision.