Two-Flop Synchronizers in Practice: Expanded Case Study

Extended case study

Milestone review flags single-bit CDC clean rate, pulse capture reliability, latency cycles around Two-Flop Synchronizers in Practice.

Background

Team believed crossings were stable until stress mode exposed intermittent anomalies.

Symptoms observed

• single-bit CDC clean rate, pulse capture reliability, latency cycles regression

• Mismatch between structural report and dynamic behavior

• Waiver debate under schedule pressure

Investigation timeline

1. Freeze design, reset, and tool configuration tags.

2. Reproduce failing scenario with minimized stimulus.

3. Map path/protocol/reset dependencies.

4. Classify root cause and containment options.

5. Execute minimal safe fix.

6. Run stress regression and review board.

Root cause

Root cause links to Two-Flop Synchronizers in Practice: A two-flop chain lowers metastability propagation risk for level signals, but only when source assumptions, pulse width, and destination sampling are respected.

Fix and validation

• Targeted RTL/protocol/reset correction

• Evidence refresh

• Signoff board decision

Lessons learned

• Treat waivers as temporary risk contracts

• Track owner and expiry

• Regression before closure

CASE STUDY — Two-Flop Synchronizers in Practice
critical issues before / after / signoff

Crossing sequence under stress

CROSSING FLOW — Two-Flop Synchronizers in Practice

source clock domain -> launch signal -> crossing structure -> destination sample
      |                    |                 |                    |
   source FF           protocol           sync / fifo         destination FF

Key metric: single-bit CDC clean rate, pulse capture reliability, latency cycles

CDC/RDC deep dive

Metastability is managed risk, not eliminated risk.

Concept diagram

METASTABILITY FLOW

async event -> first sample may metastabilize
 -> settle window
 -> downstream sample confidence

Metric graph

MTBF TREND

target MTBF ---------
current design   ____/

Reports and artifacts

• MTBF assumptions

• synchronizer inventory

• crossing class summary

• critical waivers

Mini case study

Pulse sync chosen for a level signal caused intermittent stuck state under voltage stress.

Debug branches

• Validate crossing class first

• Check pulse width assumptions

• Audit synchronizer template usage

Senior review question

Ask: what evidence proves this risk is closed for silicon, not just tool-clean?

Key takeaways

• State crossing class, assumptions, and owner with every issue.

• Run structural and dynamic regressions after each fix.

Common pitfalls

• Treating all warnings as equivalent risk.

• Waiving issues without containment evidence.

• Skipping reset and reconvergence stress after CDC fixes.

Principal CDC/RDC review addendum

A two-flop chain lowers metastability propagation risk for level signals, but only when source assumptions, pulse width, and destination sampling are respected.

Metric: single-bit CDC clean rate, pulse capture reliability, latency cycles