Reset Sequencing: Expanded Case Study

Extended case study

Milestone review flags domain bring-up order violations, dependency deadlocks, reset latency around Reset Sequencing.

Background

Team believed crossings were stable until stress mode exposed intermittent anomalies.

Symptoms observed

• domain bring-up order violations, dependency deadlocks, reset latency regression

• Mismatch between structural report and dynamic behavior

• Waiver debate under schedule pressure

Investigation timeline

1. Freeze design, reset, and tool configuration tags.

2. Reproduce failing scenario with minimized stimulus.

3. Map path/protocol/reset dependencies.

4. Classify root cause and containment options.

5. Execute minimal safe fix.

6. Run stress regression and review board.

Root cause

Reset release order violated dependency graph, enabling consumer logic before producer domain stabilized.

Fix and validation

• Targeted RTL/protocol/reset correction

• Evidence refresh

• Signoff board decision

Lessons learned

• Treat waivers as temporary risk contracts

• Track owner and expiry

• Regression before closure

CASE STUDY — Reset Sequencing
critical issues before / after / signoff

Crossing sequence under stress

CROSSING FLOW — Reset Sequencing

source clock domain -> launch signal -> crossing structure -> destination sample
      |                    |                 |                    |
   source FF           protocol           sync / fifo         destination FF

Key metric: domain bring-up order violations, dependency deadlocks, reset latency

CDC/RDC deep dive

Reset release ordering is a first-order reliability contract.

Concept diagram

RESET RELEASE FLOW

assert global -> clocks stable -> sync release per domain -> first transaction

Metric graph

BOOT STABILITY

passes per 1k boots: 920 -> 980 -> 999

Reports and artifacts

• reset dependency matrix

• RDC warning classes

• boot stress logs

• waiver aging

Mini case study

Domain B released before producer A was valid, causing rare startup deadlock.

Debug branches

• Correlate reset and clock timelines

• verify async assert/sync release

• exercise skewed release tests

Senior review question

Ask: what evidence proves this risk is closed for silicon, not just tool-clean?

Key takeaways

• State crossing class, assumptions, and owner with every issue.

• Run structural and dynamic regressions after each fix.

Common pitfalls

• Treating all warnings as equivalent risk.

• Waiving issues without containment evidence.

• Skipping reset and reconvergence stress after CDC fixes.

Principal CDC/RDC review addendum

Reset ordering enforces dependency contracts so control domains and memories become valid before downstream consumers execute.

Metric: domain bring-up order violations, dependency deadlocks, reset latency