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Course contents

  • How to Use This Course
  • CDC/RDC Metrics Reference
  • CDC/RDC Glossary
  • Reading Path
  • Metastability & Synchronizers61
  • CDC Protocols & Handshakes61
  • Reset Domain Crossing61
    • Reset Deassertion CDC
    • Reset Sequencing
      • Reset Sequencing: Mechanism
      • Reset Sequencing: Inputs & Outputs
      • Reset Sequencing: Reports & Metrics
      • Reset Sequencing: Debug Playbook
      • Reset Sequencing: Worked Example
      • Reset Sequencing: Pitfalls & Red Flags
      • Reset Sequencing: Interview Drills
      • Reset Sequencing: Review Checklist
      • Reset Sequencing: Theory Deep Dive
      • Reset Sequencing: Design Space
      • Reset Sequencing: Expanded Case Study
      • Reset Sequencing: Step-by-Step Walkthrough
      • Reset Sequencing: Comparison Matrix
      • Reset Sequencing: Software / Programmer View
      • Reset Sequencing: Silicon PPA Impact
    • RDC Structural Checks
    • Reset Debug Playbook
    • Reset Domain Crossing: Tricky Q&A
  • Reconvergence & Gray Coding61
  • CDC Signoff Methodology61
  • RDC Signoff61
  • CDC/RDC Interview Prep66
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
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‹Reset Sequencing
  1. Topics
  2. CDC & RDC
  3. Reset Domain Crossing
  4. Reset Sequencing
  5. Reset Sequencing: Pitfalls & Red Flags

CDC / RDC · All levels

Reset Sequencing: Pitfalls & Red Flags

Pitfalls & Red Flags for Reset Sequencing.

On this page

    Pitfalls and red flags

    Pitfalls & Red Flags for Reset Sequencing focuses on domain bring-up order violations, dependency deadlocks, reset latency. The goal is to convert issue observations into mechanism-backed closure decisions.

    • Two-flop synchronizer used for transactional bus crossing.

    • Waiver approved without proving containment in stressed modes.

    • Reset release checks skipped due to passing functional smoke tests.

    • Reconvergence warnings ignored as 'tool noise' without replay.

    • Dashboard green because of waivers, while critical risk remains.

    Layer responsibility check

    Diagram
    CDC/RDC OWNERSHIP LAYERS — Reset Sequencing
    
    layer                 owns                            common failure
    ------------------    -----------------------------   -----------------------------
    design intent         crossing architecture           wrong topology selected
    protocol semantics    req/ack, fifo, ordering        liveness/deadlock bugs
    reset behavior        assert/deassert sequencing      boot instability
    analysis setup        tool rules + waivers            false confidence
    signoff governance    risk acceptance + dashboard     stale critical waivers

    CDC/RDC deep dive

    Reset release ordering is a first-order reliability contract.

    Concept diagram

    Diagram
    RESET RELEASE FLOW
    
    assert global -> clocks stable -> sync release per domain -> first transaction

    Metric graph

    Diagram
    BOOT STABILITY
    
    passes per 1k boots: 920 -> 980 -> 999

    Reports and artifacts

    • reset dependency matrix

    • RDC warning classes

    • boot stress logs

    • waiver aging

    Mini case study

    Domain B released before producer A was valid, causing rare startup deadlock.

    Debug branches

    • Correlate reset and clock timelines

    • verify async assert/sync release

    • exercise skewed release tests

    Senior review question

    Ask: what evidence proves this risk is closed for silicon, not just tool-clean?

    Key takeaways

    • State crossing class, assumptions, and owner with every issue.

    • Run structural and dynamic regressions after each fix.

    Common pitfalls

    • Treating all warnings as equivalent risk.

    • Waiving issues without containment evidence.

    • Skipping reset and reconvergence stress after CDC fixes.

    Principal CDC/RDC review addendum

    Reset ordering enforces dependency contracts so control domains and memories become valid before downstream consumers execute.

    Metric: domain bring-up order violations, dependency deadlocks, reset latency

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    See also

    • Reset Sequencing: Mechanism
    • Reset Sequencing: Inputs & Outputs
    • Reset Sequencing: Reports & Metrics