VLSI DV Interview Puzzles · All levels
randomize() with Puzzles
Inline constraints are ANDed with class constraints; understand implication, conditional constraints, foreach, mode toggles, and pre/post_randomize lifecycle to predict pass/fail and outcomes.
About this puzzle set
Inline constraints are ANDed with class constraints; understand implication, conditional constraints, foreach, mode toggles, and pre/post_randomize lifecycle to predict pass/fail and outcomes.
Puzzles in this topic
diagram
1. Inline Implication Can Empty Intersection [Hard]
2. if-else in with Clause [Easy]
3. foreach Inline Constraint on Dynamic Array [Medium]
4. constraint_mode Changes Pass/Fail [Hard]
5. rand_mode(0) Freezes Value and Can Overconstrain [Medium]
6. pre_randomize Assignment vs Solver and post_randomize Call Count [Hard]Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.
Constraint solve order and dependency flow
diagram
CONSTRAINT SOLVE ORDER
rand bit [3:0] burst_len;
rand bit [7:0] addr;
constraints:
burst_len inside {[1:8]};
addr % burst_len == 0;
solve burst_len before addr;
solver picks burst_len first
then chooses addr satisfying alignment
Explicit solve order reduces ambiguity in interview puzzles.