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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
    • Constraint Solving Order Puzzles
    • Distribution Puzzles (`dist`, `:=` vs `:/`)
    • solve...before Bias Puzzles
    • randomize() with Puzzles
      • Inline Implication Can Empty Intersection
      • if-else in with Clause
      • foreach Inline Constraint on Dynamic Array
      • constraint_mode Changes Pass/Fail
      • rand_mode(0) Freezes Value and Can Overconstrain
      • pre_randomize Assignment vs Solver and post_randomize Call Count
    • Randomization & Constraint Puzzles: Tricky Q&A
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Randomization & Constraint Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Randomization & Constraint Puzzles
  4. randomize() with Puzzles

VLSI DV Interview Puzzles · All levels

randomize() with Puzzles

Inline constraints are ANDed with class constraints; understand implication, conditional constraints, foreach, mode toggles, and pre/post_randomize lifecycle to predict pass/fail and outcomes.

  • 6topics
  • 6lessons

Topics in this section

  1. 1Inline Implication Can Empty Intersection1 lesson
  2. 2if-else in with Clause1 lesson
  3. 3foreach Inline Constraint on Dynamic Array1 lesson
  4. 4constraint_mode Changes Pass/Fail1 lesson
  5. 5rand_mode(0) Freezes Value and Can Overconstrain1 lesson
  6. 6pre_randomize Assignment vs Solver and post_randomize Call Count1 lesson
On this page

    About this puzzle set

    Inline constraints are ANDed with class constraints; understand implication, conditional constraints, foreach, mode toggles, and pre/post_randomize lifecycle to predict pass/fail and outcomes.

    Puzzles in this topic

    Diagram
    1. Inline Implication Can Empty Intersection  [Hard]
    2. if-else in with Clause  [Easy]
    3. foreach Inline Constraint on Dynamic Array  [Medium]
    4. constraint_mode Changes Pass/Fail  [Hard]
    5. rand_mode(0) Freezes Value and Can Overconstrain  [Medium]
    6. pre_randomize Assignment vs Solver and post_randomize Call Count  [Hard]

    Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.

    Constraint solve order and dependency flow

    Diagram
    CONSTRAINT SOLVE ORDER
    
    rand bit [3:0] burst_len;
    rand bit [7:0] addr;
    
    constraints:
      burst_len inside {[1:8]};
      addr % burst_len == 0;
      solve burst_len before addr;
    
    solver picks burst_len first
                then chooses addr satisfying alignment
    
    Explicit solve order reduces ambiguity in interview puzzles.

    Related topics

    • Randomization & Constraint Puzzles section

    • VLSI DV Interview Puzzles hub

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    See also

    • Constraint Solving Order Puzzles
    • Distribution Puzzles (`dist`, `:=` vs `:/`)
    • solve...before Bias Puzzles