Die sizing balances area, routability, IR headroom, and timing wirelength. Utilization determines whitespace available for optimization buffers and detours.
Start from synthesized cell area plus growth guard-band per block maturity.
Account for macro halos and reserved CTS/DFT corridors before computing effective utilization.
Use congestion prediction and channel occupancy, not only global utilization, to decide go/no-go.
1. Identify where Die Size and Utilization Targets sits in the PD flow
2. Name inputs consumed and outputs produced
3. State the metric that proves success or failure
4. Link to the next downstream stage that depends on this stepNarrate Die Size and Utilization Targets using metrics, not tool commands alone.
A senior engineer does not describe Die Size and Utilization Targets as a tool step. They explain what physical assumption changed, which report becomes trustworthy after that change, and which downstream owner can now make a decision.
Which stage of the database is valid: pre-CTS, post-CTS, post-route, post-fill, or final signoff.
Which approximation is still present: estimated RC, ideal clock, abstracted macro, vectorless power, or waived PV rule.
Which downstream result depends on this mechanism: Placement quality, buffer insertion freedom, and route convergence directly depend on this decision..
You can point to Utilization by region and congestion predictor report before proposing a fix.
You can separate a local symptom from a systematic methodology issue.
You can explain why the fix is reversible, bounded, and cheaper than the alternatives.
Floorplan quality is the earliest predictor of place-and-route pain.
floorplan summary: core area, macro area, std-cell utilization
macro/channel review: pin-facing sides, halos, routing channels
power plan preview: ring width, strap pitch, follow-pin connectivity
trial route congestion: overflow around macro corners and pin fields
A 2 MB SRAM cluster is placed with pins facing the die edge. Trial route shows red overflow along the north edge. A senior PD answer is to rotate or mirror the SRAM, open the channel, and re-run trial route before attempting timing optimization.
If congestion is local to macro corners, inspect pin sides and halo width before reducing global utilization.
If IR is weak at the core edge, widen the ring or add edge straps before adding random decaps.
If timing paths cross the whole block, review pin assignment and macro orientation before post-route ECO.
Ask yourself: what single report line would prove this page's concept is either passing or failing?
You are expected to predict what your fix can break before running it.
You should recognize when the issue is methodology, not one block's implementation.
You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.
Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.
Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.
Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.
Chooses experiments by information gain and reversibility, not by habit.
States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.
Turns recurring failures into methodology guardrails, dashboards, or checklist items.
STAFF / PRINCIPAL CLOSURE NOTE
Context:
stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
tag: <database / netlist / SDC / library stack>
failing metric: <exact report line>
affected scope: <block / hierarchy / path group / power domain / region>
Hypotheses:
H1: <most likely physical or constraint mechanism>
H2: <competing explanation>
H3: <methodology or input-data issue>
Decision:
next experiment: <cheap check that can falsify H1>
fix candidate: <minimal reversible change>
rollback trigger: <metric that says the fix is wrong>
regression set: <timing / route / power / PV / DFT / package>
escalation owner: <team or reviewer>Floorplan quality is the earliest predictor of place-and-route pain. Explain not only the preferred fix, but what margin or schedule you are spending to get it.
What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?
Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?
What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?
"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."Always connect the concept back to a measurable signoff artifact.
A fix is not complete until you can name the regression checks.
Optimizing by habit instead of reading the current report.
Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.