Physical Design · All levels
Bump Map and Package Interface — Review Checklist
Review Checklist for Bump Map and Package Interface (Physical Design Integration).
Review gate
Pin map revision synced across PD and package repositories
Critical interface pins marked non-swappable
Power bump budget reviewed against IR/EM targets
Final bump map signed by package and PD owners
Smoke check (5 minutes)
Every checklist item has an owner
Failed items have mitigation or waiver ID
Definition of done for a senior owner
The exact database tag and analysis setup are recorded.
The primary metric is clean or accepted by waiver: Bump assignment matrix with electrical and package constraints.
The fix is explained by mechanism, not by tool folklore.
Regression coverage includes the obvious downstream domains: Foundry/package handoff accuracy..
Residual risk has an owner, approval path, and expiration date.
The lesson is captured as a methodology guardrail if it can recur.
Smoke check (5 minutes)
Could another engineer reproduce the conclusion from the notes alone?
Would you sign this off if the design came from another team?
Deep dive: how this shows up in real closure
Interview performance is structured closure thinking under time pressure.
Reports and artifacts to inspect
one-slide metric dashboard for the scenario
hypothesis list sorted by likelihood and cost
one report/map per experiment
regression list after the proposed fix
Mini case study
A strong answer to any scenario starts with the failing metric and signoff context. A weak answer starts with a tool command or random optimization knob.
Debug branches
If you are stuck, restate the metric and ask for corner/mode/stage.
If multiple failures exist, separate hard gates from tracked risks.
If pressured to waive, describe approval path and silicon risk.
Senior review question
Ask yourself: what single report line would prove this page's concept is either passing or failing?
What changes at 10+ years
You are expected to predict what your fix can break before running it.
You should recognize when the issue is methodology, not one block's implementation.
You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.
Principal-level review bar
Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.
What excellent looks like
Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.
Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.
Chooses experiments by information gain and reversibility, not by habit.
States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.
Turns recurring failures into methodology guardrails, dashboards, or checklist items.
Closure note template
STAFF / PRINCIPAL CLOSURE NOTE
Context:
stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
tag: <database / netlist / SDC / library stack>
failing metric: <exact report line>
affected scope: <block / hierarchy / path group / power domain / region>
Hypotheses:
H1: <most likely physical or constraint mechanism>
H2: <competing explanation>
H3: <methodology or input-data issue>
Decision:
next experiment: <cheap check that can falsify H1>
fix candidate: <minimal reversible change>
rollback trigger: <metric that says the fix is wrong>
regression set: <timing / route / power / PV / DFT / package>
escalation owner: <team or reviewer>Tradeoffs a senior engineer must discuss
Technical tradeoff
Interview performance is structured closure thinking under time pressure. Explain not only the preferred fix, but what margin or schedule you are spending to get it.
Cross-team tradeoff
What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?
Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?
What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?
Leadership communication
"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."Key takeaways
Always connect the concept back to a measurable signoff artifact.
A fix is not complete until you can name the regression checks.
Common pitfalls
Optimizing by habit instead of reading the current report.
Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.