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Course contents

  • How to Use This Course
  • PD Flow Overview — RTL to GDSII
  • Data & Libraries — What PD Receives
  • Data and Libraries49
  • Floorplanning Expanded65
  • Power Planning57
  • Placement65
  • Clock Tree Synthesis57
  • Routing65
  • Timing Closure81
  • Signal Integrity and Variation41
  • Power Signoff57
  • Physical Verification65
  • Physical Design Integration49
    • DFT Physical Implementation
    • Scan Chain Physical Effects
    • Bump Map and Package Interface
    • ESD and IO Ring Integration
    • Chip-Level Assembly Flow
      • Chip-Level Assembly Flow — Mechanism
      • Chip-Level Assembly Flow — Inputs & Outputs
      • Chip-Level Assembly Flow — Reports & Metrics
      • Chip-Level Assembly Flow — Debug Playbook
      • Chip-Level Assembly Flow — Worked Example
      • Chip-Level Assembly Flow — Pitfalls & Red Flags
      • Chip-Level Assembly Flow — Interview Drills
      • Chip-Level Assembly Flow — Review Checklist
    • IP Block Abstract Integration
    • Physical Design Integration Tricky Q&A
  • Signoff and Tapeout49
  • PD Interview Prep5
  • PD Closure Cheat Sheet
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‹Chip-Level Assembly Flow
  1. Topics
  2. Physical Design
  3. Physical Design Integration
  4. Chip-Level Assembly Flow
  5. Chip-Level Assembly Flow — Inputs & Outputs

Physical Design · All levels

Chip-Level Assembly Flow — Inputs & Outputs

Inputs & Outputs for Chip-Level Assembly Flow (Physical Design Integration).

On this page

    Inputs required

    • Netlist or DEF from prior stage

    • Technology / LEF / liberty

    • SDC and floorplan constraints

    Outputs produced

    • Updated database

    • Reports for review

    • Annotated issues for next stage

    Handoff owners

    • PD owner

    • CAD/methodology

    • Timing lead for constraint review

    Production handoff contract

    Treat Chip-Level Assembly Flow inputs as a signed contract between RTL, synthesis, CAD, IP, package, timing, and PD. A 10+ year engineer blocks execution when the contract is ambiguous instead of burning runtime on invalid databases.

    Diagram
    HANDOFF MANIFEST
      design_tag: <rtl/netlist/def tag>
      constraints_tag: <sdc/upf/mmmc tag>
      library_stack: <pdk/lib/lef/tech/qrc tag>
      signoff_corner_set: <corner/mode list>
      owner_of_truth: <team/person>
      known_risks: <open waivers or assumptions>

    Senior acceptance rules

    1. Reject mismatched views before optimization starts.

    2. Record the owner for every assumption that is not locally provable.

    3. Preserve enough metadata that another engineer can reproduce the run in six months.

    Deep dive: how this shows up in real closure

    Interview performance is structured closure thinking under time pressure.

    Reports and artifacts to inspect

    • one-slide metric dashboard for the scenario

    • hypothesis list sorted by likelihood and cost

    • one report/map per experiment

    • regression list after the proposed fix

    Mini case study

    A strong answer to any scenario starts with the failing metric and signoff context. A weak answer starts with a tool command or random optimization knob.

    Debug branches

    • If you are stuck, restate the metric and ask for corner/mode/stage.

    • If multiple failures exist, separate hard gates from tracked risks.

    • If pressured to waive, describe approval path and silicon risk.

    Senior review question

    Ask yourself: what single report line would prove this page's concept is either passing or failing?

    What changes at 10+ years

    • You are expected to predict what your fix can break before running it.

    • You should recognize when the issue is methodology, not one block's implementation.

    • You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

    Principal-level review bar

    Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

    What excellent looks like

    • Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

    • Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

    • Chooses experiments by information gain and reversibility, not by habit.

    • States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

    • Turns recurring failures into methodology guardrails, dashboards, or checklist items.

    Closure note template

    Diagram
    STAFF / PRINCIPAL CLOSURE NOTE
    
    Context:
      stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
      tag: <database / netlist / SDC / library stack>
      failing metric: <exact report line>
      affected scope: <block / hierarchy / path group / power domain / region>
    
    Hypotheses:
      H1: <most likely physical or constraint mechanism>
      H2: <competing explanation>
      H3: <methodology or input-data issue>
    
    Decision:
      next experiment: <cheap check that can falsify H1>
      fix candidate: <minimal reversible change>
      rollback trigger: <metric that says the fix is wrong>
      regression set: <timing / route / power / PV / DFT / package>
      escalation owner: <team or reviewer>

    Tradeoffs a senior engineer must discuss

    Technical tradeoff

    Interview performance is structured closure thinking under time pressure. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

    Cross-team tradeoff

    • What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

    • Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

    • What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

    Leadership communication

    Diagram
    "The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

    Key takeaways

    • Always connect the concept back to a measurable signoff artifact.

    • A fix is not complete until you can name the regression checks.

    Common pitfalls

    • Optimizing by habit instead of reading the current report.

    • Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.

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    See also

    • Chip-Level Assembly Flow — Mechanism
    • Chip-Level Assembly Flow — Reports & Metrics
    • Chip-Level Assembly Flow — Debug Playbook