Macro-heavy GPU SRAM block: architect wants 72% util, router predicts congestion in east channel.
0–5 min: Clarify macros, pins, power budget, package aspect ratio
5–15 min: Sketch floorplan — two SRAMs, channel, power ring/stripes
15–25 min: Debate util 72% vs 65% — congestion vs die cost
25–35 min: Pin assignment and strap pitch decision
35–45 min: Floorplan signoff checklist + risks to document
RUBRIC (score 1–5 each)
Metric clarity — names correct report and corner
Hypothesis quality — ordered, plausible causes
Fix discipline — minimal change, not random tweaks
Regression mindset — states what to re-run
STRONG HIRE: METRIC → hypothesis → experiment without prompting
NO HIRE: tweaks buffers without naming WNS/TNS cornerWhat if SRAM pin side faces core wall?
IR at core edge with thin ring?
Parent block abutment on north edge?
CTS spine through macro channel?
Util raised — what regression metrics?
States METRIC and corner before any fix
Orders hypotheses — does not random tweak
Names regression (corners/modes/tools) after fix
Asks clarifying questions on spec early
Silent tool clicking narrative
Fix timing before route/congestion clean
Waive DRC/LVS to meet date unprompted
Cannot explain one report line
Complete scenario in 45 min wall clock.
Self-score rubric honestly — redo weakest segment tomorrow.
After the timer ends, do a second pass without changing your answer. Mark where you named the metric, where you formed hypotheses, and where you stated regression checks.
What was the first metric you named?
Which hypothesis was cheapest to test?
Which fix carried the largest regression risk?
What would you escalate to a lead or architecture owner?
"Before I change the design, I want to confirm the failing metric, stage, corner/mode, and whether this is a hard gate or tracked risk."Scenario pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.
Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.
Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.
Chooses experiments by information gain and reversibility, not by habit.
States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.
Turns recurring failures into methodology guardrails, dashboards, or checklist items.
STAFF / PRINCIPAL CLOSURE NOTE
Context:
stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
tag: <database / netlist / SDC / library stack>
failing metric: <exact report line>
affected scope: <block / hierarchy / path group / power domain / region>
Hypotheses:
H1: <most likely physical or constraint mechanism>
H2: <competing explanation>
H3: <methodology or input-data issue>
Decision:
next experiment: <cheap check that can falsify H1>
fix candidate: <minimal reversible change>
rollback trigger: <metric that says the fix is wrong>
regression set: <timing / route / power / PV / DFT / package>
escalation owner: <team or reviewer>Interview performance is structured closure thinking under time pressure. Explain not only the preferred fix, but what margin or schedule you are spending to get it.
What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?
Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?
What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?
"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."Always connect the concept back to a measurable signoff artifact.
A fix is not complete until you can name the regression checks.
Optimizing by habit instead of reading the current report.
Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.