Which report lines prove IO Timing and Block Boundaries is healthy vs failing?
CLOSURE CHAIN
1. METRIC — name the failing report line (WNS, DRV, DRC count, IR %)
2. HYPOTHESIS — 2–3 likely causes ordered by probability
3. EXPERIMENT — one cheap check (corner, clock, report, map)
4. FIX — minimal physical or constraint change
5. REGRESSION — what you re-run and what must not regressStage summary report
Violation / slack / overflow summary
Top-N worst instances or regions
REPORT SNIPPET — IO Timing and Block Boundaries
metric_A: <value> (spec: <limit>)
metric_B: <value> (spec: <limit>)
worst_region: <name>
recommended_action: <one line>Can you name the single worst line in the report?
Can you tie that line to a physical region on the floorplan or layout?
The report is not a pass/fail artifact; it is a prioritization tool. Read interface timing budget report (set_input_delay/set_output_delay coverage) by severity, locality, trend, and fix cost before touching the design.
Confirm database tag, corner, mode, extraction state, and analysis switches.
Separate hard gates from tracked risks and cosmetic noise.
Cluster failures by physical region, hierarchy, clock domain, power domain, or rule class.
Compare against previous tag to identify new regressions, not just absolute failures.
Translate the worst line into an owner, experiment, and rollback plan.
SENIOR REPORT READOUT
worst_line: <copy exact report line>
cluster: <region/domain/rule/path-group>
delta_from_previous: <new/worse/better/same>
first_experiment: <cheap evidence-gathering action>
decision: <fix now / assign owner / waive with approval / stop release>Timing closure is a signoff matrix problem, not a single worst-path problem.
report_timing -max and -min with corner, mode, SI, and OCV enabled
path group WNS/TNS: which clock domain is actually blocking signoff
net delay percentage vs cell delay percentage
exception audit: false paths, multicycle paths, generated clocks
A -90 ps setup path has 75% net delay and crosses a macro channel. Sizing the launch flop is weak. The stronger response is to layer-promote or shorten the route, then re-run hold at the fast corner.
If net delay dominates, look for physical fixes before cell sizing.
If cell delay dominates, consider VT swap, sizing, or RTL micro-architecture.
If only one mode fails, inspect mode-specific SDC overlays and case analysis.
Ask yourself: what single report line would prove this page's concept is either passing or failing?
You are expected to predict what your fix can break before running it.
You should recognize when the issue is methodology, not one block's implementation.
You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.
Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.
Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.
Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.
Chooses experiments by information gain and reversibility, not by habit.
States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.
Turns recurring failures into methodology guardrails, dashboards, or checklist items.
STAFF / PRINCIPAL CLOSURE NOTE
Context:
stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
tag: <database / netlist / SDC / library stack>
failing metric: <exact report line>
affected scope: <block / hierarchy / path group / power domain / region>
Hypotheses:
H1: <most likely physical or constraint mechanism>
H2: <competing explanation>
H3: <methodology or input-data issue>
Decision:
next experiment: <cheap check that can falsify H1>
fix candidate: <minimal reversible change>
rollback trigger: <metric that says the fix is wrong>
regression set: <timing / route / power / PV / DFT / package>
escalation owner: <team or reviewer>Timing closure is a signoff matrix problem, not a single worst-path problem. Explain not only the preferred fix, but what margin or schedule you are spending to get it.
What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?
Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?
What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?
"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."Always connect the concept back to a measurable signoff artifact.
A fix is not complete until you can name the regression checks.
Optimizing by habit instead of reading the current report.
Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.