Physical Design · All levels

Post-Route Extraction and SPEF — Mechanism

Mechanism for Post-Route Extraction and SPEF (Timing Closure).

Physical and tool mechanism

How Post-Route Extraction and SPEF affects closure in Timing Closure.

Mechanism to narrate

  • Extraction quality directly controls STA credibility

  • Missing coupling caps can hide SI-sensitive timing failures

  • Corner-matched SPEF and liberty pairing is non-negotiable

Reference workflow

diagram
1. Identify where Post-Route Extraction and SPEF sits in the PD flow
2. Name inputs consumed and outputs produced
3. State the metric that proves success or failure
4. Link to the next downstream stage that depends on this step

Key takeaways

  • Narrate Post-Route Extraction and SPEF using metrics, not tool commands alone.

10+ year engineer lens

A senior engineer does not describe Post-Route Extraction and SPEF as a tool step. They explain what physical assumption changed, which report becomes trustworthy after that change, and which downstream owner can now make a decision.

Boundary conditions to state

  • Which stage of the database is valid: pre-CTS, post-CTS, post-route, post-fill, or final signoff.

  • Which approximation is still present: estimated RC, ideal clock, abstracted macro, vectorless power, or waived PV rule.

  • Which downstream result depends on this mechanism: timing, routing, power, PV, DFT, package, or tapeout signoff.

What top-company reviewers expect

  • You can point to SPEF coverage + RC correlation report before proposing a fix.

  • You can separate a local symptom from a systematic methodology issue.

  • You can explain why the fix is reversible, bounded, and cheaper than the alternatives.

Deep dive: how this shows up in real closure

Timing closure is a signoff matrix problem, not a single worst-path problem.

Reports and artifacts to inspect

  • report_timing -max and -min with corner, mode, SI, and OCV enabled

  • path group WNS/TNS: which clock domain is actually blocking signoff

  • net delay percentage vs cell delay percentage

  • exception audit: false paths, multicycle paths, generated clocks

Mini case study

A -90 ps setup path has 75% net delay and crosses a macro channel. Sizing the launch flop is weak. The stronger response is to layer-promote or shorten the route, then re-run hold at the fast corner.

Debug branches

  • If net delay dominates, look for physical fixes before cell sizing.

  • If cell delay dominates, consider VT swap, sizing, or RTL micro-architecture.

  • If only one mode fails, inspect mode-specific SDC overlays and case analysis.

Senior review question

Ask yourself: what single report line would prove this page's concept is either passing or failing?

What changes at 10+ years

  • You are expected to predict what your fix can break before running it.

  • You should recognize when the issue is methodology, not one block's implementation.

  • You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

Principal-level review bar

Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

What excellent looks like

  • Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

  • Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

  • Chooses experiments by information gain and reversibility, not by habit.

  • States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

  • Turns recurring failures into methodology guardrails, dashboards, or checklist items.

Closure note template

diagram
STAFF / PRINCIPAL CLOSURE NOTE

Context:
  stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
  tag: <database / netlist / SDC / library stack>
  failing metric: <exact report line>
  affected scope: <block / hierarchy / path group / power domain / region>

Hypotheses:
  H1: <most likely physical or constraint mechanism>
  H2: <competing explanation>
  H3: <methodology or input-data issue>

Decision:
  next experiment: <cheap check that can falsify H1>
  fix candidate: <minimal reversible change>
  rollback trigger: <metric that says the fix is wrong>
  regression set: <timing / route / power / PV / DFT / package>
  escalation owner: <team or reviewer>

Tradeoffs a senior engineer must discuss

Technical tradeoff

Timing closure is a signoff matrix problem, not a single worst-path problem. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

Cross-team tradeoff

  • What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

  • Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

  • What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

Leadership communication

diagram
"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

Key takeaways

  • Always connect the concept back to a measurable signoff artifact.

  • A fix is not complete until you can name the regression checks.

Common pitfalls

  • Optimizing by habit instead of reading the current report.

  • Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.