The fabric moves every byte, the clocks and resets decide when anything may move, and power decides what is awake to move it. These sections hold the most failure modes in the course, so interviewers go deep here. Every answer below needs one number or it scores generic.
Q1: Why does AXI write data have no ID. Model: write data follows the write address order per master with no interleaving, so the channel needs no tag; responses carry the ID back. Read data returns in order per ID but IDs may interleave, which is why the ordering is tracked per ID. Follow-up: what breaks if a bridge invents a write ID. Answer: response misrouting under multiple masters, so ID widths are computed from the fabric, never hand-set.
Q2: State the 4 KB rule and who enforces it. Model: a burst must not cross a 4 KB boundary because slaves decode pages; the master or converter splits, computing extra splits at each boundary. NanoSoC's stream bridge splits so the DMA never sees an illegal burst. Follow-up: what is the symptom of violation. Answer: data written into the wrong page, intermittent, caught by the protocol checker's boundary assertion.
Q3: Round robin with an idle cycle: what does it cost. Model: one idle cycle on every master change, so a 16-beat burst costs 17 cycles and efficiency is 16 over 17. With two alternating masters every burst, each master sees under half the peak. Follow-up: when does round robin starve. Answer: never by itself, but a bulk master still crowds a latency-critical one, so add bandwidth regulators or QoS classes for display-like deadlines.
Q4: Message-dependent deadlock at the top level. Model: requests and responses sharing one buffer pool stall when a full request queue blocks the responses that would free it. The fix is separate virtual channels or networks for request and response with reserved buffers. Follow-up: where does NanoSoC risk this. Answer: at the AXI-to-APB bridge under cross traffic, so read and write paths stay independent and the bridge carries a watchdog.
Q5: Derive the three clocks from the crystal. Model: 24 MHz times 32 is 768 MHz VCO, divided by 4 to 192 for the CPU and by 8 to 96 for the fabric, while the peripherals run straight off the crystal so they survive the PLL being off. Lock takes 256 peripheral clocks, 10.667 us. Follow-up: why treat the two PLL children as asynchronous. Answer: different divider roots and trees mean no phase relation at signoff, so every crossing between them gets a real synchroniser.
Q6: Release order and why the CPU is last. Model: slaves and fabric first, masters last, because a fetch issued into a fabric still in reset is lost, a lost fetch is the classic symptom. NanoSoC waits 18 system clocks for the fabric, then 8 plus 2 CPU clocks for the CPU. Follow-up: what assertion guards it. Answer: the CPU reset must not rise before the fabric reset, checked in simulation.
Q7: Async assert, sync release: what breaks otherwise. Model: release near a clock edge violates recovery and removal on some flops, so part of the block leaves reset a cycle late and the first transaction corrupts. Each domain gets its own two-flop synchroniser. Follow-up: how long must assertion last. Answer: at least 16 cycles of the domain's own clock, 666.7 ns in the slow domain.
Q8: A pulse crossing from 96 MHz to 24 MHz: safe. Model: no, a single fast pulse is shorter than two slow clocks and the sampler can miss it entirely. Use a level held until acknowledged, or a toggle with a handshake. Follow-up: what proves the fix. Answer: a ratio sweep in simulation plus the structural CDC check flagging every unsynchronised crossing.
Q9: Name the power states and what each keeps. Model: RUN everything on at 82.74 mW, IDLE with the CPU gated at 16.89, SLEEP with the switchable domain off and SRAM0 retained at 1.40. Wake jumps to the retained image instead of reloading. Follow-up: what dominates the wake time. Answer: the PLL relock at 256 slow clocks inside the 14.073 us total.
Q10: Isolation: where, what value, what order. Model: all 114 signals from the switchable domain into the always-on island clamp to 0, asserted before reset and power off, released after power good, reset and restore. The two interrupt lines are the ones designs forget. Follow-up: what is the symptom of missing isolation. Answer: X in gate-level power-aware simulation and spurious wake events in silicon.
Q11: Retention versus reload. Model: retaining SRAM0 costs 0.72 mW of leakage at 60 percent of active and buys a jump straight to the image; reloading over SPI costs 10.928 ms every wake. Retention wins whenever wake latency matters. Follow-up: what must the restore sequence guarantee. Answer: power stable, then reset released, then state restored, then isolation released, checked by a state-compare test.
Q12: Power sequencing across rails. Model: core, I/O and analog rails rise in a specified order with power-good handshakes, because the wrong order risks latch-up and wrong strap sampling. The sequencer owns the order, not software hope. Follow-up: what guards inrush. Answer: staged switch enables, daisy-chained, so all switches never slam on together.
Mechanism 2 at best: right but generic. The dividers, the bypass for the slow clock, the lock time and the asynchronous-signoff rule are what lift it to 3.