This is the most hands-on group: wiring tables, register contracts, boot ledgers and handoff checklists. The answers lean on real NanoSoC register values and on failures that integration teams meet in practice. Answers here should name registers, bits and addresses.
Q1: Level or edge for a cross-clock interrupt. Model: level, held until software clears it, because a pulse shorter than two destination clocks can be missed. NanoSoC sources are all active-high levels and the controller stores nothing, PENDING equals RAW and ENABLE. Follow-up: what goes wrong with a late clear. Answer: the handler re-enters spuriously; clear before returning or read back the clear through the posted path.
Q2: Program a DMA job correctly. Model: wait for BUSY zero, write LEN and KEY (silently ignored while busy), write CTRL 0x3 to start with interrupts enabled, wait for DONE, clear both DONE and ERR with 0x6, since GO clears DONE but not ERR. Writing 0x1 instead of 0x3 silently disables the interrupt. Follow-up: what does COUNT read mid-job. Answer: words moved so far, cleared by GO, which is how progress polling works.
Q3: The stream bridge length rule. Model: one software variable written to both SBR LEN and DMA LEN, because separate registers drift: short SBR ends the job early with ERR, long SBR stalls forever when the DMA stops accepting. The driver checks COUNT against SBR LEN after DONE. Follow-up: whose TLAST wins. Answer: the SBR's read-engine TLAST drives the early end, which is exactly the RTL behaviour, not a bug.
Q4: Interrupt storm from a level source: cause and fix. Model: the handler returns before the posted clear reaches the device, so the level is still high and the controller re-pends immediately. Fix with a read-back after the clear to flush the posted write, plus a barrier. Follow-up: how do you tell a storm from a stuck source. Answer: a storm clears between entries and the rate tracks the clear latency; a stuck source never deasserts even with the device disabled.
Q5: A DMA writes a buffer the CPU then reads: what can go stale. Model: on NanoSoC nothing, because the CPU has an instruction cache only and no data cache, and the DMA is a single-owner stream. In a system with a data cache or a coherent fabric the answer needs ownership (who may touch the buffer), cache maintenance or a coherent port, a barrier before the completion flag is read, and the order of the completion interrupt against the last data write. Follow-up: what orders the interrupt against the data. Answer: NanoSoC raises irq in the same clock the last output beat appears, but the write still has to travel through the stream bridge and fabric to memory, so the driver must not read the buffer until the bridge reports DONE, not merely the DMA.
Q1: SRAM wrapper mismatch: what do you check. Model: read latency, port polarity, byte-enable polarity, and the repair and test connections, generated from the memory compiler data rather than hand-wired. Wrong latency or polarity gives wrong data that looks like a fabric bug. Follow-up: what does BIST add. Answer: a shared controller across memories with per-macro repair fuses, owned at chip level, not per block.
Q2: Where does the 12.581 ms boot go. Model: the ROM code reads RST_CAUSE first, because a wake skips the SRAM0 clear and jumps to the retained image, while a cold boot clears 4 KB (10.667 us) and loads the image. On a cold boot: SPI load 10.928 ms at 86.9 percent, UART banner 1.387 ms at 11.0, everything else 2.1 including the 53.948 us hardware sequence. Faster boot means a faster loader, never a faster reset. Follow-up: defend the banner. Answer: sixteen characters are the cheapest field diagnostic on the board; deleting them saves 11 percent and blinds bring-up.
Q3: Secure boot chain in one minute. Model: immutable ROM authenticates the next stage against fused keys before jumping, each stage authenticating the next, with lifecycle states gating debug access. The ROM needs no crypto parameters on the whiteboard, only the chain and the failure rule: failed authentication never jumps. Follow-up: where do the keys live. Answer: one-time-programmable fuses with shadow registers loaded before first use, and trim loaded before the PLL is trusted.
Q4: ECC on memories: policy in three sentences. Model: protect both SRAMs and consider the ROM, report correctable and uncorrectable errors to the fault controller and an interrupt, and scrub on a schedule derived from the error rate. Uninitialised reads give uncorrectable errors, so on a cold boot the SRAM0 clear loop doubles as ECC initialisation; a wake skips it because SRAM0 was retained. Follow-up: poison and containment. Answer: mark known-bad data and contain it at the interconnect so one bad line cannot corrupt the fabric.
Q1: Third-party IP arrives: what do you demand. Model: the RTL, a register map in machine-readable form, clock, reset and power intent, constraints, CDC collateral, known limitations, version stamp and a verification report. Follow-up: what do you check first. Answer: port widths and address widths against the integration spec, because truncation aliases silently and everything else assumes the wires fit.
Q2: What is IP-XACT for. Model: it is the machine-readable description that generates the top netlist, the interconnect configuration and the register collateral from one source, so decode, headers and docs cannot drift. Follow-up: what still needs a human. Answer: reviewing the generated output and owning what automation cannot decide: addresses, security attributes, reset values.
Q3: Wrapper and adapter policy. Model: adapt third-party IP with wrappers at the boundary for width, protocol and clock differences, keeping the IP untouched so new versions drop in. Tie off unused inputs to a documented value and check every tie in connectivity. Follow-up: when is a wrapper wrong. Answer: when it hides a protocol violation instead of converting it, for example swallowing an error response the DMA must see.
Q4: Versioning and redelivery. Model: every collateral file carries a version stamp, acceptance runs a checklist (lint, CDC, constraints, map agreement) and redelivery re-runs it; a version bump without the checklist is rejected. Follow-up: what breaks without it. Answer: yesterday's header with today's RTL, the drift that the single-source flow exists to prevent.
It resets to 0, so interrupts are off until software writes CTRL with bit 1 set; every start must write 0x3, because writing 0x1 starts the job while leaving the interrupt disabled and the completion invisible.