Why it matters

This lesson has one job: make the partition real in gates and responses. NanoSoC carries the whole scheme in one signal: AxPROT bit 1, where 0 means secure and 1 means non-secure. Two slaves admit secure only: SRAM1 and the reset controller. One master, the SBR, defaults to non-secure. Every other slave answers either state. A non-secure access to a secure-only slave must be refused with SLVERR, never answered and never hung, and the refusal must not reveal more than the policy.

The core idea

Enforcement sits at two levels. The interconnect filter watches AxPROT beside the address decode: a non-secure access to SRAM1 selects the default error path and returns SLVERR while raising the secure fault, exactly as the decode lesson's module shows. The APB slot decoder repeats the check per slot because the DMA has no protection port of its own: the reset-controller slot refuses non-secure accesses with PSLVERR, which the bridge presents as SLVERR. The SBR is the weak point. Its CTRL non-secure bit (bit 2) resets to 1, so an uncleared SBR master is refused by SRAM1 at the first beat with STATUS error set, the miswired-attribute bug the integration section plants. That is the fail-closed half. The other half is the escape: the SBR register slot is a non-secure slot, so non-secure software can itself write CTRL.NS = 0. From then on the SBR issues secure transfers on that software's behalf and can read and write SRAM1, which the filter was supposed to keep from non-secure software. This is a confused deputy: the filter protects SRAM1 only against masters whose attribute software cannot choose. The rule is that a master's security attribute may be programmed only by an access of equal or higher privilege. On NanoSoC that means CTRL.NS must be writable from secure accesses only: either put it in a secure-only register page, or have the slot decoder refuse a non-secure write that would clear bit 2 (a non-secure write that sets it is harmless and START must stay usable). The guard module below is the second option; the filter module is the base policy. Both are compiling teaching models.

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// NanoSoC teaching values: AxPROT filter skeleton.
// prot_ns = AxPROT[1]: 1 means non-secure. Secure-only slaves refuse
// non-secure accesses with SLVERR; everything else passes through.
module nano_axprot_filter (
  input  logic       prot_ns,
  input  logic       sel_sram1,
  input  logic       sel_rstpwr,
  output logic       allow_sram1,
  output logic       allow_rstpwr,
  output logic       secure_fault,
  output logic [1:0] err_resp
);
  assign allow_sram1  = sel_sram1 & ~prot_ns;
  assign allow_rstpwr = sel_rstpwr & ~prot_ns;
  assign secure_fault = (sel_sram1 | sel_rstpwr) & prot_ns;
  assign err_resp     = 2'b10; // SLVERR
endmodule

// Guard for the SBR CTRL register (slot offset 0x0C, bit 2 = NS).
// prot_ns is the attribute the decoder receives with the access (APB3 has
// no PPROT, so it travels as a sideband from the bridge).
// A non-secure write that would CLEAR NS is refused with PSLVERR and does
// not reach the register; a non-secure write that sets NS, or a START
// write that keeps NS = 1, passes.
module nano_sbr_ns_guard (
  input  logic        psel_sbr,
  input  logic        pwrite,
  input  logic        prot_ns,
  input  logic [11:0] paddr,
  input  logic [31:0] pwdata,
  output logic        write_ok,
  output logic        pslverr
);
  logic hits_ctrl, clears_ns;
  assign hits_ctrl = (paddr[7:0] == 8'h0C);
  assign clears_ns = ~pwdata[2];
  assign pslverr   = psel_sbr & pwrite & hits_ctrl & prot_ns & clears_ns;
  assign write_ok  = psel_sbr & pwrite & ~pslverr;
endmodule

The script has two parts. First it walks the address decode table of the memory map (the source of truth: base, size and the secure-only flag of each slave, the same table the filter is generated from) and compares every slave in both states, plus one probe in each of the four address holes, against an expected table written out by hand, cell by cell. A mutated decode table, with the secure flag dropped from the reset controller, must be caught. Second it models the SBR escape: non-secure software writes CTRL.NS = 0 and then copies out of SRAM1, once on v1 and once with the guard.

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decode = [  # (slave, base, size, secure_only): the memory map
    ("ROM", 0x0000_0000, 0x4000, False), ("SRAM0", 0x2000_0000, 0x1_0000, False),
    ("SRAM1", 0x2001_0000, 0x1_0000, True), ("DMA", 0x4000_0000, 0x1000, False),
    ("SBR", 0x4000_1000, 0x1000, False), ("UART", 0x4000_2000, 0x1000, False),
    ("SPI", 0x4000_3000, 0x1000, False), ("GPIO", 0x4000_4000, 0x1000, False),
    ("INTC", 0x4000_5000, 0x1000, False), ("RSTPWR", 0x4000_6000, 0x1000, True),
]
def respond(addr, ns, table):
    for name, base, size, secure_only in table:
        if base <= addr < base + size:
            return "SLVERR" if (secure_only and ns) else "OK"
    if 0x4000_0000 <= addr <= 0x4000_FFFF:
        return "SLVERR"  # hole H3: the APB decoder's default slave
    return "DECERR"      # holes H1, H2, H4: the interconnect's default slave
expected = {  # (slave, secure access, non-secure access), written by hand
    "ROM": ("OK", "OK"), "SRAM0": ("OK", "OK"), "SRAM1": ("OK", "SLVERR"),
    "DMA": ("OK", "OK"), "SBR": ("OK", "OK"), "UART": ("OK", "OK"), "SPI": ("OK", "OK"),
    "GPIO": ("OK", "OK"), "INTC": ("OK", "OK"), "RSTPWR": ("OK", "SLVERR"),
}
def mismatches(table):
    bad = []
    for name, base, size, secure_only in decode:
        probe = base + 0x10
        got = (respond(probe, 0, table), respond(probe, 1, table))
        if got != expected[name]:
            bad.append((name, got))
    return bad
assert mismatches(decode) == [], mismatches(decode)
holes = {0x0000_4000: "DECERR", 0x2002_0000: "DECERR", 0x4000_7000: "SLVERR", 0x4001_0000: "DECERR"}
for addr, want in holes.items():
    assert respond(addr, 0, decode) == respond(addr, 1, decode) == want, hex(addr)
mutated = [(n, b, s, False if n == "RSTPWR" else so) for n, b, s, so in decode]
assert [name for name, _ in mismatches(mutated)] == ["RSTPWR"]
print("access matrix: 20 cases and 4 holes agree with the hand-written expectation; a mutated table is caught")

class Sbr:
    def __init__(self, guard):
        self.ns, self.guard = 1, guard   # CTRL.NS resets to 1
    def write_ctrl(self, value, writer_ns):
        if self.guard and writer_ns and not (value >> 2) & 1:
            return "PSLVERR"
        self.ns = (value >> 2) & 1
        return "OK"
    def copy_from_sram1(self):
        return respond(0x2001_0000, self.ns, decode)
v1 = Sbr(guard=False)
assert v1.copy_from_sram1() == "SLVERR"               # fail-closed reset
assert v1.write_ctrl(0x0, writer_ns=1) == "OK"        # non-secure software clears NS
assert v1.copy_from_sram1() == "OK", "the escape: SRAM1 read through the SBR"
fixed = Sbr(guard=True)
assert fixed.write_ctrl(0x0, writer_ns=1) == "PSLVERR"
assert fixed.copy_from_sram1() == "SLVERR"
assert fixed.write_ctrl(0x1, writer_ns=1) == "PSLVERR"  # a START write that clears NS is refused too
assert fixed.write_ctrl(0x5, writer_ns=1) == "OK"       # START with NS kept at 1 still works
assert fixed.write_ctrl(0x0, writer_ns=0) == "OK" and fixed.copy_from_sram1() == "OK"  # secure software may clear it
print("v1: non-secure CTRL.NS = 0 opens SRAM1; guarded: refused, secure software unaffected")
print("PASS: matrix matches, mutation caught, SBR escape reproduced on v1 and closed by the guard")

What the review looks for

• The partition table names every slave in both states with the responder and response of each refusal.

• Secure filtering is visible beside each decoder with its own fault output, never folded silently into a select.

• The SBR non-secure default is documented with the driver rule (secure software clears the bit before touching SRAM1) and with the hardware rule that only a secure access may write it.

Verify and debug

Walk the whole matrix from both states in simulation: twenty accesses, two SLVERRs, eighteen successes, with the secure fault asserted exactly twice. Then leave the SBR non-secure bit at its reset value and run a DMA copy out of SRAM1: the first beat must return SLVERR and set the SBR status error with the DMA staying busy. Finally run the negative test for the escape: from non-secure software write CTRL.NS = 0, check the write is refused (or has no effect), then start a DMA copy out of SRAM1 and confirm it still fails; the same test must pass (the copy succeeds) when the write comes from secure software. If a secure-only slave answers non-secure software, the filter enable for that slot is at reset default.

Related topics

• Next: Lifecycle States and Debug Locking

• Verification: SoC and Software-Driven Tests