DenseChip

SoC Integration · All levels

Package SI/PI Contracts: Review Checklist

Review Checklist for Package SI/PI Contracts.

Review checklist

Review Checklist for Package SI/PI Contracts focuses on SI/PI margin violations, package-driven timing regressions. The goal is to map symptoms to boundary contracts, owner actions, and regression-proof closure.

  • Baseline manifest and revision are explicit.

  • Boundary contracts for this topic are current and approved.

  • Ownership map covers all open issues.

  • Focused and full regression evidence both exist.

  • Residual risks are either closed or bounded via waiver policy.

  • Owners signed: SI/PI owner, package architect, signoff owner.

Signoff ownership

diagram
OWNERSHIP MAP — Package SI/PI Contracts

artifact             owner
-----------------    -----------------
primary owner     SI/PI owner
co-owner          package architect
review owner      signoff owner

No top-level issue should remain ownerless beyond one review cycle.

SoC deep dive

Package assumptions must be treated as first-class chip constraints.

Concept diagram

diagram
PACKAGE CO-DESIGN
die io <-> package routing <-> board constraints

Metric graph

diagram
PACKAGE RISK MIX
SI margin █████
power integrity ████
lane mapping ███

Reports and artifacts

  • bump map revision log

  • SI/PI margin report

  • IO co-design checklist

  • package bring-up failures

Mini case study

Link degradation on product board came from package routing assumptions not reflected in pre-silicon model.

Debug branches

  • Compare package model versions

  • Audit lane mapping

  • Correlate SI/PI margins to failures

Senior review question

Ask: what baseline, owner, and artifact prove this topic is truly closed?

Key takeaways

  • State baseline manifest and owner with every closure metric.

  • Run cross-domain regression after every top-level fix.

Common pitfalls

  • Comparing results across different manifests.

  • Unowned issues slipping through review cycles.

  • Waiving risks without expiry and validation plan.

Principal SoC review addendum

Package SI/PI constraints define return paths, impedance, and noise budgets that must be reflected in chip-level assumptions.

Metric: SI/PI margin violations, package-driven timing regressions

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