Package SI/PI Contracts: Silicon PPA Impact

Silicon PPA and closure impact

Package-driven issues are expensive and often discovered too late.

Area drivers

• Guardband margins

• late ECO spillover

Power drivers

• Emergency frequency guards

• clocking overhead

Timing impact

• Cross-domain path regressions

• late closure churn

PD consequences

• Route congestion from top-level fixes

• package-driven detours

Verification burden

• Re-validation of waived assumptions

PPA RISK — Package SI/PI Contracts
area/power/timing confidence vs integration velocity

PPA takeaways

• Integration discipline reduces expensive late-stage silicon risk.

Design option PPA snapshot

BEFORE / AFTER FIX — Package SI/PI Contracts

risk index
 0 |                    --- target
40 |    ● regression
65 |         ● before fix
20 |              ● after fix
    +-------------------------------> iteration
Always verify collateral, regression suite, and owner signoff.

SoC deep dive

Package assumptions must be treated as first-class chip constraints.

Concept diagram

PACKAGE CO-DESIGN
die io <-> package routing <-> board constraints

Metric graph

PACKAGE RISK MIX
SI margin █████
power integrity ████
lane mapping ███

Reports and artifacts

• bump map revision log

• SI/PI margin report

• IO co-design checklist

• package bring-up failures

Mini case study

Link degradation on product board came from package routing assumptions not reflected in pre-silicon model.

Debug branches

• Compare package model versions

• Audit lane mapping

• Correlate SI/PI margins to failures

Senior review question

Ask: what baseline, owner, and artifact prove this topic is truly closed?

Key takeaways

• State baseline manifest and owner with every closure metric.

• Run cross-domain regression after every top-level fix.

Common pitfalls

• Comparing results across different manifests.

• Unowned issues slipping through review cycles.

• Waiving risks without expiry and validation plan.

Principal SoC review addendum

Package SI/PI constraints define return paths, impedance, and noise budgets that must be reflected in chip-level assumptions.

Metric: SI/PI margin violations, package-driven timing regressions