STA Mastery · All levels

Useful Skew Tradeoffs: Software / Programmer View

Software / Programmer View for Useful Skew Tradeoffs.

RTL / implementation view

RTL pipelining vs PD sizing is the classic architecture trade.

What designers feel

  • Surprise timing after RTL 'small' change

  • Clock domain bugs

RTL structure impact

  • Pipeline depth

  • Reset and clock gating

  • Boundary flop placement

Synthesis interaction

  • Retiming constraints

  • Don't care optimization vs STA

RTL-side mitigations

  • Register boundaries

  • Clean clocking

  • Review SDC with RTL changes

diagram
RTL — Useful Skew Tradeoffs
// pipeline stage added -> check new reg2reg path group WNS

Layer the driver touches

diagram
STA OWNERSHIP LAYERS — Useful Skew Tradeoffs

layer              owns                         failure mode
----------------   --------------------------   ---------------------
constraints        clocks, IO, exceptions       false violations
implementation     cells, nets, placement       real path delay
extraction         SPEF/RC corners              view mismatch
signoff policy     derate, MMMC matrix          margin disputes
closure           ECO order, regression        fix breaks other corner

STA deep dive

ECO without regression is a coin flip.

Concept diagram

diagram
ECO LOOP

failing path -> fix -> setup check -> hold check -> SI -> MMMC matrix

Metric graph

diagram
ECO PROGRESS

WNS
 0 |              o target
-50|        o
-100|   o baseline
    +-----------------> ECO #

Reports and artifacts

  • pre/post WNS

  • hold delta

  • leakage delta

  • ECO ticket log

Mini case study

48-hour tapeout crunch: VT swap fixed setup; hold fixed with route on short path — order mattered.

Debug branches

  • Never ship setup-only proof

  • Logical ECO needs equivalence

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

  • State corner, mode, view, and database tag with every slack claim.

  • Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

  • Comparing STA runs with different SPEF or SDC tags.

  • Broad false_path to green-wash violations.

  • Setup-only ECO without hold check.

Principal STA review addendum

Intentional clock skew can borrow setup time but increases hold risk and clock tree complexity; useful skew is a negotiated margin.

Metric: skew budget used, hold impact, clock tree power