STA Mastery · All levels

SI ECO Fix Order

SI Timing & Noise: SI fixes use spacing, shielding, sizing, and reroute; order matters because a setup fix can worsen hold or noise elsewhere.

What this topic teaches

SI ECO Fix Order is about converting constraints and path rules into measurable slack. SI fixes use spacing, shielding, sizing, and reroute; order matters because a setup fix can worsen hold or noise elsewhere. The hard part is never the textbook inequality; it is proving, under the right corner/mode/view, which layer — constraint, view, or implementation — broke the contract.

The senior-engineer question

When post-ECO SI WNS recovery, reroute count, spacing violations cleared moves, can you identify the failing path group, the STA layer, the responsible owner, and the smallest experiment that proves the root cause?

diagram
STA CLOSURE FLOW — SI ECO Fix Order

constraints (SDC)
        |
        v
timing graph (cell + net delays)
        |
        v
MMMC scenarios (corner x mode x view)
        |
        v
variation + SI adjustments
        |
        v
slack (WNS/TNS) -> ECO -> regression

Debug rule: always state corner, mode, view, and database tag with slack.

Picture the timing closure flow

Start every study session by drawing the behavior before reading signals. The diagrams below are the mental models to reproduce on a whiteboard.

SI fix priority

diagram
SI ECO ORDER
1. spacing / shield on worst aggressors
2. victim upsize (if delta delay)
3. reroute victim to quiet layer
4. re-run SI + setup + hold matrix

Timing path sequence

diagram
TIMING PATH — SI ECO Fix Order

launch FF --logic stages--> capture FF
     |                           |
  launch clock                capture clock
     |                           |
  required: arrival < capture_edge - setup
  metric: post-ECO SI WNS recovery, reroute count, spacing violations cleared

Who owns which layer

diagram
STA OWNERSHIP LAYERS — SI ECO Fix Order

layer              owns                         failure mode
----------------   --------------------------   ---------------------
constraints        clocks, IO, exceptions       false violations
implementation     cells, nets, placement       real path delay
extraction         SPEF/RC corners              view mismatch
signoff policy     derate, MMMC matrix          margin disputes
closure           ECO order, regression        fix breaks other corner

Evidence to collect

  • Primary metric: post-ECO SI WNS recovery, reroute count, spacing violations cleared.

  • Primary artifact: ECO change list, before/after SI report, regression matrix.

  • Owners to bring into review: PD owner, SI owner, STA lead.

  • Spec clause or requirement ID for every constraint claim.

  • One failing report_timing excerpt and one reduced path that isolates the rule.

Ownership map

diagram
OWNERSHIP MAP — SI ECO Fix Order

artifact              owner
----------------      -----------------
timing report       PD owner
SDC/constraint      SI owner
implementation      STA lead

Every WNS cluster needs a named owner before ECO.

Subpages in this topic

Each topic is taught across mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

  • State corner, mode, and view with every slack number.

  • Separate constraint bugs, view mismatches, and real path delays before ECO.

  • Run setup and hold plus full MMMC after every change.

Common pitfalls

  • Comparing runs with different SPEF or SDC tags.

  • Broad false_path to hide violations.

  • Setup-only ECO without hold regression.

STA deep dive

Coupling makes delay a function of neighbors, not just wire RC.

Concept diagram

diagram
SI ON VICTIM

victim net delay = base_RC + coupling_from_aggressors

Metric graph

diagram
DELTA DELAY ON CRITICAL PATHS

no SI   ████████  1.2ns
with SI ██████████  1.35ns  (+150ps)

Reports and artifacts

  • delta delay report

  • aggressor list

  • noise peaks

  • SI WNS delta

Mini case study

Setup fixed by upsize but SI worsened — spacing ECO on bus bits recovered margin.

Debug branches

  • Re-run SI after every timing ECO

  • Shield wide switching buses

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

  • State corner, mode, view, and database tag with every slack claim.

  • Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

  • Comparing STA runs with different SPEF or SDC tags.

  • Broad false_path to green-wash violations.

  • Setup-only ECO without hold check.