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Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
  • Constraints & SDC Fundamentals20
  • Delay Graph & Path Analysis16
  • Beyond Setup and Hold16
  • Multi-Corner Multi-Mode Signoff16
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
    • Delta Delay Mechanism
    • Noise and Glitch Analysis
      • Glitch Height and Width
      • Noise Immunity
      • Functional Failure Risk
      • Noise Review
    • SI ECO Fix Order
    • SI Signoff Reports
  • ECO and Closure16
  • STA Debug Playbook16
  • STA Interview Prep26
  • Capstone Timing Signoff Lab4
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‹Crosstalk and Noise
  1. Topics
  2. Static Timing Analysis
  3. Crosstalk and Noise
  4. Noise and Glitch Analysis

Part 7 · Crosstalk and Noise · All levels

Noise and Glitch Analysis

What happens when an aggressor switches next to a net that is not switching: the size of the glitch, whether the receiver tolerates it, which receivers matter, and how a noise review is run.

  • 4topics
  • 4lessons

Delta delay concerns nets that are switching. Noise analysis concerns nets that are not: a quiet victim next to a switching aggressor receives a pulse through the coupling capacitance. If the pulse is large enough and long enough, the receiving cell can respond to it as if it were a real transition. This topic covers how glitch height and width arise, how receivers are rated against them, why some receivers are far more dangerous than others, and the review process.

Lesson

After it you can...

Glitch Height and Width

Compute the peak of a coupled glitch.

Noise Immunity

Compare a glitch with a receiver's tolerance curve.

Functional Failure Risk

Prioritise noise violations by receiver type.

Noise Review

Gate signoff on a noise summary.

Check yourself Why can a glitch on a quiet net be worse than a delay change?

A delay change only moves a transition. A glitch can create a transition that should not exist, for example a spurious clock edge or reset, and corrupt state.

Interview

Be able to explain why noise on a clock or reset net is treated more strictly than noise on a data net.

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See also

  • Delta Delay Mechanism
  • SI ECO Fix Order
  • SI Signoff Reports