STA Mastery · All levels

Noise Glitch Analysis

SI Timing & Noise: Beyond delta delay, aggressors can inject glitches on quiet victims; noise analysis checks functional thresholds on sensitive inputs.

What this topic teaches

Noise Glitch Analysis is about converting constraints and path rules into measurable slack. Beyond delta delay, aggressors can inject glitches on quiet victims; noise analysis checks functional thresholds on sensitive inputs. The hard part is never the textbook inequality; it is proving, under the right corner/mode/view, which layer — constraint, view, or implementation — broke the contract.

The senior-engineer question

When noise peak, glitch width, functional fail rate on SI-critical nets moves, can you identify the failing path group, the STA layer, the responsible owner, and the smallest experiment that proves the root cause?

diagram

STA CLOSURE FLOW — Noise Glitch Analysis

constraints (SDC)
        |
        v
timing graph (cell + net delays)
        |
        v
MMMC scenarios (corner x mode x view)
        |
        v
variation + SI adjustments
        |
        v
slack (WNS/TNS) -> ECO -> regression

Debug rule: always state corner, mode, view, and database tag with slack.

Picture the timing closure flow

Start every study session by drawing the behavior before reading signals. The diagrams below are the mental models to reproduce on a whiteboard.

Glitch on quiet victim

diagram

VOLTAGE
  ^     glitch peak
  |    /\
  |___/  \_____ victim (should stay quiet)
      ^ may cause false toggle on input FF

Timing path sequence

diagram

TIMING PATH — Noise Glitch Analysis

launch FF --logic stages--> capture FF
     |                           |
  launch clock                capture clock
     |                           |
  required: arrival < capture_edge - setup
  metric: noise peak, glitch width, functional fail rate on SI-critical nets

Who owns which layer

diagram

STA OWNERSHIP LAYERS — Noise Glitch Analysis

layer              owns                         failure mode
----------------   --------------------------   ---------------------
constraints        clocks, IO, exceptions       false violations
implementation     cells, nets, placement       real path delay
extraction         SPEF/RC corners              view mismatch
signoff policy     derate, MMMC matrix          margin disputes
closure           ECO order, regression        fix breaks other corner

Evidence to collect

Primary metric: noise peak, glitch width, functional fail rate on SI-critical nets.
Primary artifact: noise report, victim waveform, fix list (spacing/shielding).
Owners to bring into review: SI owner, RTL owner, STA owner.
Spec clause or requirement ID for every constraint claim.
One failing report_timing excerpt and one reduced path that isolates the rule.

Ownership map

diagram

OWNERSHIP MAP — Noise Glitch Analysis

artifact              owner
----------------      -----------------
timing report       SI owner
SDC/constraint      RTL owner
implementation      STA owner

Every WNS cluster needs a named owner before ECO.

Subpages in this topic

Each topic is taught across mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

State corner, mode, and view with every slack number.
Separate constraint bugs, view mismatches, and real path delays before ECO.
Run setup and hold plus full MMMC after every change.

Common pitfalls

Comparing runs with different SPEF or SDC tags.
Broad false_path to hide violations.
Setup-only ECO without hold regression.

STA deep dive

Coupling makes delay a function of neighbors, not just wire RC.

Concept diagram

diagram

SI ON VICTIM

victim net delay = base_RC + coupling_from_aggressors

Metric graph

diagram

DELTA DELAY ON CRITICAL PATHS

no SI   ████████  1.2ns
with SI ██████████  1.35ns  (+150ps)

Reports and artifacts

delta delay report
aggressor list
noise peaks
SI WNS delta

Mini case study

Setup fixed by upsize but SI worsened — spacing ECO on bus bits recovered margin.

Debug branches

Re-run SI after every timing ECO
Shield wide switching buses

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.

Practice this lesson