Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
  • Constraints & SDC Fundamentals20
  • Delay Graph & Path Analysis16
  • Beyond Setup and Hold16
  • Multi-Corner Multi-Mode Signoff16
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
    • Delta Delay Mechanism
      • Coupling and Aggressors
      • Switching Windows
      • Delta Delay Arithmetic
      • Setup Versus Hold Impact
    • Noise and Glitch Analysis
    • SI ECO Fix Order
    • SI Signoff Reports
  • ECO and Closure16
  • STA Debug Playbook16
  • STA Interview Prep26
  • Capstone Timing Signoff Lab4
Loading lesson

‹Delta Delay Mechanism
  1. Topics
  2. Static Timing Analysis
  3. Crosstalk and Noise
  4. Delta Delay Mechanism
  5. Setup Versus Hold Impact

Part 7 · Crosstalk and Noise · All levels

Setup Versus Hold Impact

Crosstalk slows data and clock paths when aggressors switch against them and speeds them up when they switch with them; setup and hold use opposite extremes.

On this page

    Why it matters

    Delta delay has a sign. For setup the analysis assumes the worst slowdown on data and on the launch clock path, and the worst speedup on the capture clock. For hold the signs reverse. Hold violations from crosstalk are easy to miss because they are small and appear most often in fast corners with SI on.

    Which direction hurts which check

    Check

    Data path

    Launch clock path

    Capture clock path

    Setup

    Aggressor against victim: slower data arrival (bad)

    Aggressor against victim: later launch (bad)

    Aggressor with victim: earlier capture clock (bad)

    Hold

    Aggressor with victim: faster data arrival (bad)

    Aggressor with victim: earlier launch (bad)

    Aggressor against victim: later capture clock (bad)

    example.py
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    # Hold check at one flop, picoseconds (illustrative).
    hold_nominal = 30.0
    data_speedup = 8.0            # aggressor switching with the data net speeds the data path
    clock_delay_increase = 5.0    # aggressor against the capture clock net delays the capture clock
    hold_with_si = hold_nominal - data_speedup - clock_delay_increase
    assert hold_with_si == 17.0
    # Setup check at the same flop
    setup_nominal = 40.0
    data_slowdown = 12.0
    clock_speedup = 4.0           # aggressor with the capture clock makes it arrive earlier
    setup_with_si = setup_nominal - data_slowdown - clock_speedup
    assert setup_with_si == 24.0
    total_hold_loss = hold_nominal - hold_with_si
    total_setup_loss = setup_nominal - setup_with_si
    assert (total_hold_loss, total_setup_loss) == (13.0, 16.0)
    print("PASS: hold slack", hold_nominal, "->", hold_with_si, "; setup slack", setup_nominal, "->", setup_with_si)

    The same flop loses 13 ps of hold slack and 16 ps of setup slack to crosstalk, from four different effects in this model: data and capture clock, slow and fast. The launch clock path mirrors the capture path with the opposite sign, as the table shows, and is left out of the numbers above. Note that the aggressors in the two calculations are not the same: each check assumes the worst-case behaviour of its own aggressors, and a physical aggressor cannot be doing both at once. Correct SI analysis keeps the two checks separate and does not combine their deltas.

    What the review looks for

    • Hold reports exist with SI on, in every corner used for hold signoff, and are clean.

    • Clock nets are included in the SI analysis, not only data nets: a victim clock net moves capture time directly.

    • Fixes for hold (adding delay) are re-checked for the crosstalk they may introduce on the new nets.

    Common pitfall

    Signing off hold without SI because hold is considered a fast-corner, no-crosstalk problem. Speedups from crosstalk are exactly what turns thin hold slack negative.

    Interview

    Say that setup uses the slowdown on data and the speedup on capture clock, and hold the reverse.

    Check yourself If an aggressor switches with the capture clock net, does that help or hurt hold?

    It speeds up the capture clock, which makes it arrive earlier: that helps hold slightly and hurts setup. It is the aggressors that switch against the capture clock that hurt hold.

    Related topics

    • Delta Delay Arithmetic

    Previous

    109 / 183

    Next: Noise and Glitch Analysis

    Up next

    Up nextNoise and Glitch Analysis

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Coupling and Aggressors
    • Switching Windows