A violation count treats all noise violations as equal. They are not. A glitch at a data pin that happens when the flop is not capturing does nothing. A glitch on a flop clock pin can clock the flop at the wrong time; one on an asynchronous reset can clear it. Ranking by receiver type puts the dangerous ones first.
Receiver | What a glitch can do | Policy |
|---|---|---|
Clock pin | Spurious clock edge: state changes at the wrong time | Fix any violation; require a margin |
Asynchronous reset or set | Spurious reset or set of a flop | Fix any violation; require a margin |
Latch enable | Latch opens briefly and captures data | Fix any violation; require a margin |
Flop data pin | Only matters if it overlaps the capture window | Fix violations; check windows |
Combinational input | Propagates, and only matters if it reaches one of the above | Fix if it reaches a critical receiver |
# (net, receiver, margin in volts: allowed height minus glitch height)
nets = [("n1", "flop_D", 0.20), ("n2", "clock_pin", 0.05), ("n3", "async_reset", 0.08),
("n4", "latch_enable", 0.12), ("n5", "flop_D", -0.03), ("n6", "flop_D", 0.02)]
critical = {"clock_pin", "async_reset", "latch_enable"}
required_critical_margin = 0.10
must_fix = [(n, r, m) for n, r, m in nets
if (r in critical and m < required_critical_margin) or (r not in critical and m < 0)]
order = [n for n, r, m in sorted(must_fix, key=lambda t: (t[1] not in critical, t[2]))]
watch = [n for n, r, m in nets if (n, r, m) not in must_fix and m < 0.05]
assert order == ["n2", "n3", "n5"]
assert watch == ["n6"]
print("PASS: fix in this order", order, "; watch list", watch)Six nets, one with a data-pin violation and two critical-receiver nets that pass the library curve but fall short of the stricter 0.10 V margin. The critical ones go first: n2 at 0.05 V and n3 at 0.08 V are not violations on paper, but a glitch that reaches a clock or reset pin is not worth betting on. The data-pin violation n5 comes next; n6, passing with 0.02 V, is watched but not fixed. The ordering (n2, n3 before the real data violation n5) reflects the stricter policy for critical receivers. The 0.10 V requirement is an example policy, not a standard.
Noise results are broken down by receiver class, and critical classes have their own margin and their own sign-off.
Every critical receiver has a margin, not just a pass or fail.
Combinational receivers are traced forward to see whether the glitch can reach a critical pin.
The glitch can propagate through the logic to a clock, reset or latch pin, or to a data pin during its capture window; whether it matters depends on where it ends up.