SI ECO Fix Order: Software / Programmer View

RTL / implementation view

Bus encoding and switching activity affect aggressor alignment.

What designers feel

• Surprise timing after RTL 'small' change

• Clock domain bugs

RTL structure impact

• Pipeline depth

• Reset and clock gating

• Boundary flop placement

Synthesis interaction

• Retiming constraints

• Don't care optimization vs STA

RTL-side mitigations

• Register boundaries

• Clean clocking

• Review SDC with RTL changes

RTL — SI ECO Fix Order
// pipeline stage added -> check new reg2reg path group WNS

Layer the driver touches

STA OWNERSHIP LAYERS — SI ECO Fix Order

layer              owns                         failure mode
----------------   --------------------------   ---------------------
constraints        clocks, IO, exceptions       false violations
implementation     cells, nets, placement       real path delay
extraction         SPEF/RC corners              view mismatch
signoff policy     derate, MMMC matrix          margin disputes
closure           ECO order, regression        fix breaks other corner

STA deep dive

Coupling makes delay a function of neighbors, not just wire RC.

Concept diagram

SI ON VICTIM

victim net delay = base_RC + coupling_from_aggressors

Metric graph

DELTA DELAY ON CRITICAL PATHS

no SI   ████████  1.2ns
with SI ██████████  1.35ns  (+150ps)

Reports and artifacts

• delta delay report

• aggressor list

• noise peaks

• SI WNS delta

Mini case study

Setup fixed by upsize but SI worsened — spacing ECO on bus bits recovered margin.

Debug branches

• Re-run SI after every timing ECO

• Shield wide switching buses

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

SI fixes use spacing, shielding, sizing, and reroute; order matters because a setup fix can worsen hold or noise elsewhere.

Metric: post-ECO SI WNS recovery, reroute count, spacing violations cleared