SI Signoff Reports: Silicon PPA Impact

Silicon PPA and closure impact

Extraction quality and route layers drive delta delay accuracy.

Area drivers

• Upsize cells

• Buffer insertion

• Shield wires

Power drivers

• VT swap leakage

• Clock tree power for skew

Timing impact

• Net delay on critical routes

• SI delta delay

PD consequences

• Congestion limits sizing

• Layer promotion for nets

Verification burden

• ECO equivalence

• SI re-signoff

PPA — SI Signoff Reports
area/power/timing/closure-time tradeoff

PPA takeaways

• ECO has PPA cost

• Signoff is multi-corner

Design option PPA snapshot

BEFORE / AFTER ECO — SI Signoff Reports

WNS (ps)
  0 |                    --- target
-50 |    ● regressed
-80 |         ● before ECO
-20 |              ● after ECO
    +-------------------------------> ECO iteration
Prove setup AND hold moved safely.

STA deep dive

Coupling makes delay a function of neighbors, not just wire RC.

Concept diagram

SI ON VICTIM

victim net delay = base_RC + coupling_from_aggressors

Metric graph

DELTA DELAY ON CRITICAL PATHS

no SI   ████████  1.2ns
with SI ██████████  1.35ns  (+150ps)

Reports and artifacts

• delta delay report

• aggressor list

• noise peaks

• SI WNS delta

Mini case study

Setup fixed by upsize but SI worsened — spacing ECO on bus bits recovered margin.

Debug branches

• Re-run SI after every timing ECO

• Shield wide switching buses

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

SI signoff aggregates delta delay and noise against foundry rules and product margin; reports must map to fix ownership.

Metric: SI-clean path %, remaining aggressor violations, signoff waiver count