One module, several widths

A width parameter turns one adder into a family of adders. The flow elaborates the same source at each width and checks each result.

Each run below holds a single top module with one addition. The generic netlist of each run therefore holds exactly one $add cell.

The runnable flow

The script reads the parameterised adder inline, runs generic synthesis, and asserts the adder count at each width. It ends with one log PASS line.

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read_verilog <<EOV
module top #(parameter W = 4) (input [W-1:0] a, b, output [W:0] s);
  assign s = a + b;
endmodule
EOV
hierarchy -top top
proc
opt_clean
check
select -assert-count 1 t:$add
stat
design -reset
read_verilog <<EOV
module top #(parameter W = 8) (input [W-1:0] a, b, output [W:0] s);
  assign s = a + b;
endmodule
EOV
hierarchy -top top
proc
opt_clean
check
select -assert-count 1 t:$add
stat
log PASS: width-parameterised adder gives one adder cell at widths 4 and 8

Assertions are the proof

stat prints the generic census into the log for human readers. select -assert-count pins the counts, so a wrong claim fails the run instead of the review.

Common mistakes

Related topics

• Logging and QoR extraction

• Cell libraries and Liberty