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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
    • Equivalence Checking
      • Combinational Equivalence of RTL and Netlist
      • Key Points and Black Boxes
      • Retiming and FSM Recoding
      • Reading an Equivalence Failure
      • Constants and Brute Force
    • Incremental Compile and ECO
    • Physical-Aware Synthesis and Handoff
  • Flows and Debugging15
  • Interview and Judgment11
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‹Equivalence Checking
  1. Topics
  2. Logic Synthesis
  3. Verification, ECO and Handoff
  4. Equivalence Checking
  5. Constants and Brute Force

Part 7 · Verification, ECO and Handoff · Intermediate

Constants and Brute Force

Tied inputs, unreachable cases, and exhaustive brute force on three inputs.

On this page

    Constants and tied inputs

    Configuration pins and tied-off inputs shrink the input space. Both sides must apply the same tie-offs before comparison, or constants compare as divergences.

    A proved tie-off propagates into the cone and simplifies it. The proof then covers the smaller space exactly.

    Tie-off

    Space

    Proof covers

    No ties, 3 inputs

    8 vectors.

    All 8 vectors.

    One pin tied, 2 free

    4 vectors.

    The 4 vectors with the tie applied.

    Two pins tied, 1 free

    2 vectors.

    Both values of the free pin.

    Handling of unreachable cases

    Some vectors cannot occur: a one-hot bus never shows two bits set, and a mode pin never toggles in mission logic. Treating them as comparable creates false failures.

    Each unreachable case needs a stated constraint on both sides. Without it the solver flags a vector the design never sees.

    Unreachable case

    Constraint

    If omitted

    Two-hot on a one-hot bus

    At most one bit set.

    A false divergence on two-hot vectors.

    Illegal mode code

    Mode stays within valid codes.

    A false divergence on unused codes.

    Reset-active plus enable

    Enable is low during reset.

    A false divergence on the overlap.

    Brute force over three inputs

    On three inputs every vector can be enumerated directly. The program below replays the RTL against the mutated block from the previous lesson over all eight vectors.

    example.py
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    import sys
    
    def gold(a, b, c):
        return (a & b) | ((1 ^ a) & c)
    
    def mutated(a, b, c):
        return (a & b) | (a & c)
    
    bad = []
    agree = 0
    for a in (0, 1):
        for b in (0, 1):
            for c in (0, 1):
                g = gold(a, b, c)
                m = mutated(a, b, c)
                if g == m:
                    agree += 1
                else:
                    bad.append((a, b, c, g, m))
    
    if not len(bad) == 3:
        print("FAIL: want 3 differing vectors, got " + str(len(bad)))
        sys.exit(1)
    if not agree == 5:
        print("FAIL: want 5 agreeing vectors, got " + str(agree))
        sys.exit(1)
    if not (gold(0, 0, 1) == 1 and mutated(0, 0, 1) == 0):
        print("FAIL: vector 001 must give RTL 1 and mutated 0")
        sys.exit(1)
    if (0, 0, 1, 1, 0) not in bad or (0, 1, 1, 1, 0) not in bad or (1, 0, 1, 0, 1) not in bad:
        print("FAIL: differing set must be 001, 011 and 101")
        sys.exit(1)
    
    print("PASS: 8 vectors give 5 agreements and 3 differences at 001, 011 and 101")

    The program visits each vector once through nested loops over 2 by 2 by 2. Its checks pin the agreement count, the difference count, and all three differing vectors.

    Diagram
    input space doubles per free input: 2^1 = 2, 2^2 = 4, 2^3 = 8, 2^4 = 16
    3 inputs enumerate as nested loops: 2 x 2 x 2 = 8 vectors
    brute force visits every vector once, so no case is skipped

    Common mistakes

    Common pitfall

    Brute force scales as two to the power of free inputs. It settles tiny cones and cross-checks a solver vector, but it never replaces the proof on wide logic.

    Interview

    Likely probes: when enumeration is legitimate.

    • Tiny cones enumerate fully; wide cones do not.

    • Tie-offs shrink the space before counting vectors.

    • Unreachable cases need stated constraints first.

    Check yourself One input is tied, leaving two free. How many vectors does brute force visit?

    Four. Two free inputs give 2^2, which is 4 vectors with the tie applied.

    Check yourself The program reports differences at 001, 011 and 101. What do those vectors share, and why?

    All three have c=1 with a and b not both 1. At c=1 the RTL gives b when a=1 and 1 when a=0, while the mutated block gives b OR c when a=1 and 0 when a=0, so they agree only at a=1 and b=1.

    Related topics

    • Reading a failure

    • Incremental compile and ECO

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    Next: Incremental Compile and ECO

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    See also

    • Combinational Equivalence of RTL and Netlist
    • Key Points and Black Boxes
    • Retiming and FSM Recoding