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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
    • Equivalence Checking
      • Combinational Equivalence of RTL and Netlist
      • Key Points and Black Boxes
      • Retiming and FSM Recoding
      • Reading an Equivalence Failure
      • Constants and Brute Force
    • Incremental Compile and ECO
    • Physical-Aware Synthesis and Handoff
  • Flows and Debugging15
  • Interview and Judgment11
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‹Equivalence Checking
  1. Topics
  2. Logic Synthesis
  3. Verification, ECO and Handoff
  4. Equivalence Checking
  5. Key Points and Black Boxes

Part 7 · Verification, ECO and Handoff · Intermediate

Key Points and Black Boxes

Primary outputs, flop boundaries and black boxes as the comparison points.

On this page

    Where comparisons happen

    Every comparison endpoint is a key point. Primary inputs feed cones, primary outputs end them, and register outputs cut sequential feedback into combinational pieces.

    A cone with no key point at its boundary cannot be checked in isolation. The boundary set must be complete before the run starts.

    Key point

    Role

    If missing

    Primary input

    Shared stimulus for both sides.

    Cones start at different logic and agree by accident.

    Register output

    Cuts feedback so the remaining logic is combinational.

    Sequential loops enter the cone and the proof does not apply.

    Primary output

    Observed result of each cone.

    A divergence escapes unobserved.

    Black boxes

    Memories, analog blocks and third-party macros are boxed: their internals are skipped. Each box becomes an ideal boundary with the same ports on both sides.

    Boxing trades coverage for capacity. Logic inside a box is trusted, never proven.

    Situation

    Treatment

    Consequence

    SRAM macro

    Box with identical ports both sides.

    Address decode and wrapper logic still compare.

    Analog block

    Box at its digital interface.

    Only the digital handshake compares.

    Unmapped hard block

    Box until a model exists.

    Its cone endpoints move to the box pins.

    Constants at the boundary

    Tie-offs must match on both sides of every key point. A pin tied to 1 in RTL and left floating in the netlist is a real divergence, not tool noise.

    The same holds for box pins. Constant straps on a boxed macro are part of the comparison.

    Boundary

    RTL

    Netlist must show

    Mode pin

    Tied to 1.

    The same constant 1.

    Box enable

    Driven by logic.

    The same driver cone, not a strap.

    Unused input

    Tied to 0.

    The same constant 0.

    Common mistakes

    Common pitfall

    Boxing a block that changed between RTL and netlist hides the change. Re-check the box list after every ECO or macro swap.

    Interview

    Likely probes: what gets boxed, and what boxing costs.

    • Boxed logic is trusted, so its bugs escape the check.

    • Box pins stay as key points with matched constants.

    • Wrapper logic around a box still compares normally.

    Check yourself A memory macro is boxed. A bug sits in its surrounding address decoder. Does the check catch it?

    Yes. The wrapper is outside the box, so its cones compare as usual. Only the macro interior is skipped.

    Check yourself The RTL ties a mode pin to 1 and the netlist ties it to 0. Is that a mismatch?

    Yes. Constants are compared values. The cones genuinely differ on every vector using that pin.

    Related topics

    • Constants and brute force

    • Simulation-synthesis mismatch

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    See also

    • Reading an Equivalence Failure
    • Constants and Brute Force