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Course contents

  • Start Here4
  • UVM Foundations14
  • UVM Phases & Simulation Lifecycle26
  • Factory & Configuration15
  • Transaction-Level Modeling (TLM)13
  • UVM Sequences & Stimulus21
  • UVM Agents & Protocol VIP21
    • Agent Architecture
    • Reusable VIP: Active, Passive and Protocol Agents
    • Error and Fault Injection
      • Sequence-Directed Faults
      • Driver Injection Hooks
      • Callbacks versus Factory Overrides
      • Checking Expected Faults
    • Agent Patterns: Slaves, Reset, Interrupts and Pipelines
  • Environment & Test Classes11
  • Checking & Coverage in UVM21
  • UVM Register Abstraction Layer (RAL)22
  • Advanced UVM in Practice13
  • Debug & Regression10
  • Coding Practice47
  • Verification in Industry Practice10
  • Senior Prep: Architecture, Leadership and Interviews32
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‹UVM Agents & Protocol VIP
  1. Topics
  2. UVM Verification
  3. UVM Agents & Protocol VIP
  4. Error and Fault Injection

Part 6 · Agents & Protocol IP · Intermediate

Error and Fault Injection

How a UVM bench injects faults on purpose, from legal-but-wrong stimulus to driver overrides and callbacks, and how it proves the DUT reacted.

  • 4topics
  • 4lessons
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    A testbench that only sends good traffic proves half the spec. The DMA's spec also says what happens when things go wrong: an access to an unmapped register answers with PSLVERR, and a packet that ends before LEN words ends the job with STATUS.ERR and an interrupt. Error injection is how you exercise those paths on purpose, and error checking is how you prove the DUT reacted, without letting the bench forgive real bugs along the way.

    What you will be able to do

    • Decide whether a fault needs any new code at all, or is just a legal stimulus choice a sequence can make.

    • Inject a fault at the driver with a virtual hook and a factory override, without editing a single sequence, and clone before you modify.

    • Choose between callbacks and factory overrides, and write the three pieces of a callback correctly.

    • Predict expected errors from what the monitors observe, so the scoreboard checks the DUT's error response instead of being told to look away.

    Where a fault can enter the DMA bench

    Flow diagram: a sequence, a factory override and a callback all feed the stream driver's pre_drive hook; the driver drives the DMA; monitors report beats, output words and STATUS reads to a scoreboard that predicts DONE or ERR.
    Faults enter through the sequence (legal but wrong stimulus) or through the driver's hook (an override or a callback). The scoreboard predicts the DUT's error response from what the monitors saw.

    The lessons, in order

    Lesson

    What it covers

    Sequence-Directed Faults

    The DMA's two error responses, faults a legal item can express, fault intent in item fields, and clearing ERR afterwards.

    Driver Injection Hooks

    axis_truncating_driver: a virtual pre_drive hook, clone before modify, and a type override set before the env is built.

    Callbacks versus Factory Overrides

    Why overrides do not compose, and a truncation callback with uvm_register_cb, uvm_do_callbacks and add/delete done right.

    Checking Expected Faults

    Why the data scoreboard passes a truncated job, predicting ERR from observed traffic, timeouts for missed faults, and demoting expected errors.

    Tip

    Every fault test needs two checks: that the fault really happened on the pins, and that the DUT responded as the spec says. A test that checks only the second can pass with no fault injected at all.

    Related topics

    • Up: Agents & Protocol VIP

    • Previous topic: Reusable VIP

    • Next topic: Agent Patterns

    PreviousNext: Sequence-Directed Faults

    Up next

    Up nextSequence-Directed Faults

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    See also

    • Agent Architecture
    • Reusable VIP: Active, Passive and Protocol Agents
    • Agent Patterns: Slaves, Reset, Interrupts and Pipelines