Env architecture interview bank.
[INT][SENIOR][UVM-CODE]
Q: What goes in env vs test?
A:
Env: agents, scoreboard, cfg. Test: sequences, objections, factory overrides.
FOLLOW-UP TRAP: Sequences hardcoded in env.[INT][SENIOR][UVM-CODE]
Q: Virtual sequencer placement?
A:
In env — holds sub sequencer handles.
FOLLOW-UP TRAP: In test only without env ref.[INT][SENIOR][UVM-CODE]
Q: Passive agent wiring?
A:
Monitor only — connect ap to scoreboard in env connect.
FOLLOW-UP TRAP: Driver in passive agent.[INT][SENIOR][UVM-CODE]
Q: Coverage in env vs test?
A:
Env: protocol coverage. Test: scenario coverage.
FOLLOW-UP TRAP: All in test only.[INT][SENIOR][UVM-CODE]
Q: Multi-agent env sketch 20 min?
A:
boxes: 2 agents, sb, vseq, cfg — connect arrows.
FOLLOW-UP TRAP: Code every class.[INT][SENIOR][UVM-CODE]
Q: Reusable VIP integration?
A:
Wrap VIP agent; config_db for VIP cfg; don't modify VIP internals.
FOLLOW-UP TRAP: Fork VIP source.[INT][SENIOR][UVM-CODE]
Q: Env config object?
A:
uvm_object cfg with active flags, widths — set from test.
FOLLOW-UP TRAP: ifdef everywhere.[INT][SENIOR][UVM-CODE]
Q: Scoreboard in env?
A:
Yes — standard for check components.
FOLLOW-UP TRAP: Scoreboard in test.[INT][SENIOR][UVM-CODE]
Q: Predictor placement?
A:
Env between stimulus analysis and scoreboard.
FOLLOW-UP TRAP: Inside driver.[INT][SENIOR][UVM-CODE]
Q: TLM connect in env connect_phase?
A:
All monitor→sb/cov connections here.
FOLLOW-UP TRAP: In test run_phase.[INT][SENIOR][UVM-CODE]
Q: Env topology print?
A:
uvm_top.print_topology() for debug.
FOLLOW-UP TRAP: Manual hierarchy only.[INT][SENIOR][UVM-CODE]
Q: Sub-env for subsystem?
A:
Block env embedded in chip env — hierarchical envs.
FOLLOW-UP TRAP: Flat one env 50 agents.[INT][SENIOR][UVM-CODE]
Q: Test library pattern?
A:
Multiple tests extend base_test; env shared.
FOLLOW-UP TRAP: Duplicate env per test file.[INT][SENIOR][UVM-CODE]
Q: IRQ monitor agent?
A:
Passive monitor agent — ap to sb or irq collector.
FOLLOW-UP TRAP: IRQ in APB driver.[INT][SENIOR][UVM-CODE]
Q: Reg model in env?
A:
ral model built in env; adapter on bus agent.
FOLLOW-UP TRAP: RAL only in test.[INT][SENIOR][UVM-CODE]
Q: Env vs top module?
A:
top: interfaces, run_test. env: UVM hierarchy.
FOLLOW-UP TRAP: DUT in env.[INT][SENIOR][UVM-CODE]
Q: Parameterize env?
A:
cfg object not parameters on env class.
FOLLOW-UP TRAP: generate ifdefs.[INT][SENIOR][UVM-CODE]
Q: 3-agent APB mock?
A:
master active, slave passive monitor, reg in env — 20 min sketch.
FOLLOW-UP TRAP: Full RTL detail.[INT][SENIOR][UVM-CODE]
Q: Closure talk in interview?
A:
Coverage plan + regression + waivers — after env sketch.
FOLLOW-UP TRAP: Only components no closure.[INT][SENIOR][UVM-CODE]
Q: Staff-level env difference?
A:
Explicit cfg, domains, reuse, debug hooks.
FOLLOW-UP TRAP: Same as junior env box.