Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • Start Here4
  • UVM Foundations14
  • UVM Phases & Simulation Lifecycle26
  • Factory & Configuration15
  • Transaction-Level Modeling (TLM)13
  • UVM Sequences & Stimulus21
  • UVM Agents & Protocol VIP21
  • Environment & Test Classes11
  • Checking & Coverage in UVM21
  • UVM Register Abstraction Layer (RAL)22
  • Advanced UVM in Practice13
  • Debug & Regression10
  • Coding Practice47
    • How to Use This Course
    • Whiteboard Delivery Framework
    • Scoreboard Coding
    • Monitor & Driver Coding
    • Sequences Coding
    • TLM & Analysis
    • RAL & Adapters
    • Factory & config_db
    • Phases & Objections
      • Objection Count & Drain Time
      • Phase Jump & Domain Sync
      • Run-Time Sub-Phases
      • Phases Tricky Q&A
    • Env & Test Architecture
    • Debug Broken Testbench
    • Mock Interview Sets
    • Senior UVM Coding Cheat Sheet
  • Verification in Industry Practice10
  • Senior Prep: Architecture, Leadership and Interviews32
Loading lesson

‹Phases & Objections
  1. Topics
  2. UVM Verification
  3. Coding Practice
  4. Phases & Objections
  5. Objection Count & Drain Time

UVM Coding Practice · Senior

Objection Count & Drain Time

raise/drop pairing and pipeline drain.

On this page

    Interview prompt

    Test hangs at end — walk through objection debug.

    Diagram
    WHITEBOARD CHAIN
    
    1. DECLARE    interfaces / types / ports you need
    2. SKELETON   class extends + utils macro + key methods
    3. MECHANISM  fill one critical method while narrating
    4. PITFALL    name one bug juniors make on this pattern
    5. TEST       how you would smoke-test the component

    Reference sketch (≤40 lines)

    design.sv
    1
    2
    3
    4
    5
    6
    task run_phase(uvm_phase phase);
      phase.raise_objection(this);
      seq.start(env.sqr);
      phase.phase_done.set_drain_time(this, 100);
      phase.drop_objection(this);
    endtask

    Mechanism to narrate

    • Draw timeline: raise → stimulus → drain → drop

    • If hang: print who still has objection (UVM objection trace)

    • Pipelined DUT needs drain_time before drop

    Smoke test (5 minutes)

    • Normal test ends within timeout.

    • Remove drop_objection — sim hangs (repro leak).

    • Zero drain on pipelined DUT — compare with 100ns drain.

    Common pitfalls

    • Missing drop_objection.

    • No drain on pipelined DUT.

    • Seq and test both raise without policy.

    Previous

    221 / 280

    Next: Phase Jump & Domain Sync

    Up next

    Up nextPhase Jump & Domain Sync

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Run-Time Sub-Phases
    • Phases Tricky Q&A