Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutRoadmapCareersInternshipsFAQContactPrivacyTerms
Skip to lesson

Course contents

  • Start Here4
  • UVM Foundations14
  • UVM Phases & Simulation Lifecycle26
  • Factory & Configuration15
  • Transaction-Level Modeling (TLM)13
  • UVM Sequences & Stimulus21
  • UVM Agents & Protocol VIP21
  • Environment & Test Classes11
  • Checking & Coverage in UVM21
  • UVM Register Abstraction Layer (RAL)22
  • Advanced UVM in Practice13
  • Debug & Regression10
  • Coding Practice47
    • How to Use This Course
    • Whiteboard Delivery Framework
    • Scoreboard Coding
      • Ordered FIFO Compare
      • Out-of-Order Reorder Buffer
      • Multi-Stream Merge
      • Predictor & Reference Model
      • Scoreboard Tricky Q&A
    • Monitor & Driver Coding
    • Sequences Coding
    • TLM & Analysis
    • RAL & Adapters
    • Factory & config_db
    • Phases & Objections
    • Env & Test Architecture
    • Debug Broken Testbench
    • Mock Interview Sets
    • Senior UVM Coding Cheat Sheet
  • Verification in Industry Practice10
  • Senior Prep: Architecture, Leadership and Interviews32
Loading lesson

←Scoreboard Coding
  1. Topics
  2. UVM Verification
  3. Coding Practice
  4. Scoreboard Coding
  5. Scoreboard Tricky Q&A
On this page

    UVM Coding PracticeSenior

    Scoreboard Tricky Q&A

    20 senior scoreboard interview questions with outlines and follow-up traps.

    Scoreboard interview bank

    Answer aloud using MECHANISM / PITFALL / WHEN structure.

    FIFO depth for scoreboard — how do you size it?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: FIFO depth for scoreboard — how do you size it?
    
    A:
    MECHANISM: depth ≥ max outstanding transactions (pipeline + bus latency). MOTIVATION: underrun drops compares; overrun drops exp. PITFALL: fixed depth 1 on multi-outstanding bus.
    
    FOLLOW-UP TRAP: They ask what happens on overflow — must say drop/count/fatal policy.

    Out-of-order AXI responses — compare strategy?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Out-of-order AXI responses — compare strategy?
    
    A:
    MECHANISM: keyed queue by ID or search exp_q for matching tag. WHEN: AXI read/write resp IDs. PITFALL: head-only compare on OOO bus.
    
    FOLLOW-UP TRAP: Stale ID after timeout — need age-out policy.

    Scoreboard vs protocol checker?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Scoreboard vs protocol checker?
    
    A:
    SCOREBOARD: data integrity vs reference. CHECKER: protocol rules (valid/ready, state). Both can run; checker usually in monitor.
    
    FOLLOW-UP TRAP: Using scoreboard for X-prop — wrong tool.

    Predictor before scoreboard — why?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Predictor before scoreboard — why?
    
    A:
    Predictor transforms stimulus to expected txn stream; scoreboard only compares. Decouples ref model from check.
    
    FOLLOW-UP TRAP: Predictor inside scoreboard write — harder to reuse.

    Partial beat compare on narrow bus?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Partial beat compare on narrow bus?
    
    A:
    Compare byte lanes with mask from strb/keep; don't compare full 32-bit when only 1 byte valid.
    
    FOLLOW-UP TRAP: Endianness on sub-word access.

    Reset mid-transaction in FIFO?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Reset mid-transaction in FIFO?
    
    A:
    Flush both queues on reset assertion; ignore compares until idle. Document policy in scoreboard.
    
    FOLLOW-UP TRAP: Compare after reset with stale exp entry.

    Mismatch reporting — UVM_ERROR vs counter?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Mismatch reporting — UVM_ERROR vs counter?
    
    A:
    ERROR for first N mismatches then FATAL or cap — avoids log flood. Store txn snapshot in message.
    
    FOLLOW-UP TRAP: No txn print — debug nightmare.

    Two analysis imports — naming convention?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Two analysis imports — naming convention?
    
    A:
    exp_imp / act_imp or dut/analysis naming — consistent with team style. uvm_analysis_imp macro per stream.
    
    FOLLOW-UP TRAP: Same imp class for both — write() collision confusion.

    Reference model in same class as scoreboard?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Reference model in same class as scoreboard?
    
    A:
    Separate predictor component feeding exp stream — scoreboard stays compare-only.
    
    FOLLOW-UP TRAP: Monolithic scoreboard — interview red flag for reuse.

    Latency-insensitive compare?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Latency-insensitive compare?
    
    A:
    FIFO absorbs delay; compare when both sides have data. For fixed latency, optional shift register on exp.
    
    FOLLOW-UP TRAP: Assuming zero latency bus.

    How to debug exp/act size mismatch?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: How to debug exp/act size mismatch?
    
    A:
    Log queue sizes each compare; dump head txn both sides; check monitor vs predictor reset.
    
    FOLLOW-UP TRAP: Only logging act side.

    Multi-master same scoreboard?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Multi-master same scoreboard?
    
    A:
    Tag txn with master ID; separate FIFOs or keyed merge before compare.
    
    FOLLOW-UP TRAP: Interleaved streams without key.

    Scoreboard in passive-only env?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Scoreboard in passive-only env?
    
    A:
    Yes — monitor provides act; predictor or RM provides exp. No driver required for check.
    
    FOLLOW-UP TRAP: Thinking scoreboard needs sequencer.

    Functional coverage on scoreboard?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Functional coverage on scoreboard?
    
    A:
    Cover mismatch types, queue depth bins, timeout paths — optional subscriber on mismatch event.
    
    FOLLOW-UP TRAP: Coverage only in monitor — miss check paths.

    Endianness in compare?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Endianness in compare?
    
    A:
    Normalize in monitor/predictor to canonical host order before push to FIFO.
    
    FOLLOW-UP TRAP: Raw bus order in scoreboard.

    When to use scoreboard vs SVA?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: When to use scoreboard vs SVA?
    
    A:
    Scoreboard for data/equivalence; SVA for temporal protocol and one-cycle rules.
    
    FOLLOW-UP TRAP: SVA for full packet compare — too heavy.

    Pipeline scoreboard stages?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Pipeline scoreboard stages?
    
    A:
    Multiple FIFO stages matching DUT pipeline depth; compare at commit stage.
    
    FOLLOW-UP TRAP: Compare at fetch stage vs retire.

    Soft compare vs hard compare?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Soft compare vs hard compare?
    
    A:
    Soft: log warning for known benign diff. Hard: UVM_ERROR. Document waiver list.
    
    FOLLOW-UP TRAP: All mismatches ERROR in bring-up.

    Scoreboard performance — large queues?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Scoreboard performance — large queues?
    
    A:
    Cap depth, sample compares, disable verbose print in regression.
    
    FOLLOW-UP TRAP: Unbounded queue on stress test — memory blow-up.

    Whiteboard scoreboard in 15 minutes?

    Diagram
    [INT][SENIOR][UVM-CODE]
    
    Q: Whiteboard scoreboard in 15 minutes?
    
    A:
    Skeleton + two imps + two queues + compare_head in 10 min; pitfall + test in 5 min.
    
    FOLLOW-UP TRAP: Spending 15 min on macros only.
    Previous

    193 / 280

    Next: Monitor & Driver Coding

    Up next

    Up nextMonitor & Driver Coding

    Sign in to save progress

    Practice this lessonPrevious lessonReport an error

    See also

    • Ordered FIFO Compare
    • Out-of-Order Reorder Buffer
    • Multi-Stream Merge