Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutRoadmapCareersInternshipsFAQContactPrivacyTerms
Skip to lesson

Course contents

  • Start Here4
  • UVM Foundations14
  • UVM Phases & Simulation Lifecycle26
  • Factory & Configuration15
  • Transaction-Level Modeling (TLM)13
  • UVM Sequences & Stimulus21
  • UVM Agents & Protocol VIP21
  • Environment & Test Classes11
  • Checking & Coverage in UVM21
  • UVM Register Abstraction Layer (RAL)22
  • Advanced UVM in Practice13
  • Debug & Regression10
  • Coding Practice47
    • How to Use This Course
    • Whiteboard Delivery Framework
    • Scoreboard Coding
    • Monitor & Driver Coding
    • Sequences Coding
      • Basic Sequence Body
      • Layered Virtual Sequence
      • Grab, Lock & Ungrab
      • Sequence Library Arbitration
      • Sequences Tricky Q&A
    • TLM & Analysis
    • RAL & Adapters
    • Factory & config_db
    • Phases & Objections
    • Env & Test Architecture
    • Debug Broken Testbench
    • Mock Interview Sets
    • Senior UVM Coding Cheat Sheet
  • Verification in Industry Practice10
  • Senior Prep: Architecture, Leadership and Interviews32
Loading lesson

←Sequences Coding
  1. Topics
  2. UVM Verification
  3. Coding Practice
  4. Sequences Coding
  5. Basic Sequence Body
On this page

    UVM Coding PracticeSenior

    Basic Sequence Body

    start_item, finish_item, objections.

    Interview prompt

    Write a sequence that sends 10 randomized pkt items on a sequencer.

    Diagram
    WHITEBOARD CHAIN
    
    1. DECLARE    interfaces / types / ports you need
    2. SKELETON   class extends + utils macro + key methods
    3. MECHANISM  fill one critical method while narrating
    4. PITFALL    name one bug juniors make on this pattern
    5. TEST       how you would smoke-test the component

    Reference sketch (≤40 lines)

    design.sv
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    class pkt_seq extends uvm_sequence #(pkt);
      `uvm_object_utils(pkt_seq)
      virtual task body();
        repeat (10) begin
          pkt req = pkt::type_id::create("req");
          start_item(req);
          assert(req.randomize());
          finish_item(req);
        end
      endtask
    endclass

    Buggy snippet — critique verbally

    design.sv
    start_item(req);
    req.addr = 5; // forgot randomize
    finish_item(req);

    Code lab drill

    After reading, try Code lab exercise uvm-l8-int-basic-seq — topic reference: /topics/uvm/coding-practice/sequences/basic-sequence-body

    Smoke test (5 minutes)

    • Run seq — 10 items on bus.

    • UVM transaction log count = 10.

    Common pitfalls

    • No randomize.

    • Objection leak if test waits forever.

    • finish_item before drive completes if rsp required.

    Previous

    204 / 280

    Next: Layered Virtual Sequence

    Up next

    Up nextLayered Virtual Sequence

    Sign in to save progress

    Practice this lessonPrevious lessonReport an error

    See also

    • Grab, Lock & Ungrab
    • Sequence Library Arbitration
    • Sequences Tricky Q&A