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Course contents

  • Start Here4
  • UVM Foundations18
  • UVM Phases & Simulation Lifecycle94
  • Factory & Configuration37
  • Transaction-Level Modeling (TLM)42
  • UVM Sequences & Stimulus44
  • UVM Agents & Protocol VIP71
  • Environment & Test Classes55
    • Environment Architecture
    • Environment Composition Hub: Scaling Reusable Env Topologies
    • Scoreboard + Coverage Hub: Integrated Checking Pipelines
      • Analysis Port Fan-In: Merging Streams into Checkers
      • Scoreboard Env Wiring: Connect-Phase Contracts
      • Coverage Subscriber in Env: Placement and Fan-Out Strategy
      • Dual-Stream Checking: Expected vs Observed Correlation
      • Env Checking Pipeline: Stage-Based Compare Architecture
      • Checking Integration Debug: Ordered Triage for Silent Failures
    • Tests: Base Classes, Selection and Startup
    • Config Distribution Hub: Test-to-Env Policy Propagation
    • Virtual Sequencer Hub: Env-Level Multi-Agent Coordination
    • Plusargs & Test Selection Hub: Runtime Control Without Recompile
    • End-of-Test Hub: Objections, Readiness, and Fail-Fast Shutdown
    • Top Module Hub: Startup Contracts from HDL to UVM
  • Checking & Coverage in UVM37
  • UVM Register Abstraction Layer (RAL)53
  • Advanced UVM in Practice44
  • Debug & Regression10
  • Coding Practice47
  • Senior Prep: Architecture, Leadership and Interviews92
  • Verification in Industry Practice10
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‹Scoreboard + Coverage Hub: Integrated Checking Pipelines
  1. Topics
  2. UVM Verification
  3. Environment & Test Classes
  4. Scoreboard + Coverage Hub: Integrated Checking Pipelines
  5. Env Checking Pipeline: Stage-Based Compare Architecture

Part 7 · Environment & Tests · Intermediate

Env Checking Pipeline: Stage-Based Compare Architecture

Structuring checking into staged pipeline blocks for normalization, correlation, compare, and diagnostics at environment scale.

On this page

    Stage architecture

    Large projects benefit from explicit checker stages. Stage boundaries make ownership, performance, and debug responsibilities clear.

    Diagram
    [ENV][UVM][CHECK] pipeline stages
    
    stage 0: ingest
    stage 1: normalize
    stage 2: correlate
    stage 3: compare
    stage 4: classify + report
    
    for each stage:
      input counter
      output counter
      drop/reject reason counter
    design.sv
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    function txn pipeline_normalize(txn in);
      txn out = in.clone();
      out.addr = out.addr & 'hFFFF;
      out.byte_en = sanitize_be(out.byte_en);
      norm_hits++;
      return out;
    endfunction
    • Stage counters localize failures immediately.

    • Normalization logic should be pure and deterministic.

    • Stage ownership can be split across team members safely.

    Key takeaways

    • Pipelines scale checker complexity without losing debug clarity.

    • Countered stage boundaries make regressions observable.

    Common pitfalls

    • Monolithic compare functions with hidden preprocessing.

    • No stage-level counters, forcing wave-only debug.


    Applied Patterns

    Capture stage transition metadata so each mismatch includes full provenance.

    Diagram
    [CHECK] provenance fields
    
    txn.debug.stage0_time
    txn.debug.stage1_time
    txn.debug.stage2_time
    txn.debug.stage3_time
    txn.debug.source_stream
    txn.debug.correlation_id
    
    diagnostic policy:
      include provenance in all mismatch reports
    design.sv
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    function void stamp_stage(txn t, string stage_name);
      t.debug.last_stage = stage_name;
      t.debug.last_time  = $time;
    endfunction
    • Provenance data converts vague mismatches into actionable reports.

    • Keep provenance lightweight to avoid throughput impact.

    • Standardize stage names across scoreboards.


    Integration Drilldown

    Run stage-isolation tests that bypass one stage at a time and verify expected failure signatures.

    Diagram
    [CHECK] stage isolation
    
    test A: bypass normalize
      expect format mismatches
    
    test B: bypass correlate
      expect missing-pair errors
    
    test C: bypass compare
      expect suspiciously zero mismatches warning

    Key takeaways

    • Stage isolation proves each pipeline block is genuinely active.

    Common pitfalls

    • Assuming stage enable flags work without targeted tests.

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    See also

    • Analysis Port Fan-In: Merging Streams into Checkers
    • Scoreboard Env Wiring: Connect-Phase Contracts
    • Coverage Subscriber in Env: Placement and Fan-Out Strategy