reg_adapter bus2reg: Prediction from Monitor Items

Why bus2reg is as important as reg2bus

reg2bus controls what you ask the bus to do; bus2reg controls what RAL believes actually happened. Prediction quality depends on bus2reg correctness.

bus2reg usually runs inside uvm_reg_predictor after monitor traffic arrives. For reads, this path is the authoritative source of returned data in many environments.

[BUS] [RAL] prediction pipeline

  monitor observes protocol item
      |
      v
  predictor receives bus item
      |
      v
  adapter.bus2reg(bus_item, rw)
      |
      v
  predictor updates register mirror via rw fields

• Map observed read data from monitor item to rw.data reliably.

• Set rw.status accurately; NOT_OK must propagate for failing transactions.

• Handle direction consistently, especially in mixed response channels.

Predictor wiring with bus2reg

A robust frontdoor setup uses explicit prediction: disable auto-predict on the map and connect monitor analysis port to predictor bus_in.

class reg_env extends uvm_env;
  `uvm_component_utils(reg_env)
  my_reg_block                   rm;
  apb_reg_adapter                adapter;
  apb_agent                      apb;
  uvm_reg_predictor #(apb_item)  pred;

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    rm      = my_reg_block::type_id::create("rm");
    adapter = apb_reg_adapter::type_id::create("adapter");
    apb     = apb_agent::type_id::create("apb", this);
    pred    = uvm_reg_predictor#(apb_item)::type_id::create("pred", this);
    rm.build();
    rm.lock_model();
  endfunction

  function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);

    rm.default_map.set_sequencer(apb.sqr, adapter);
    rm.default_map.set_auto_predict(0);

    pred.map     = rm.default_map;
    pred.adapter = adapter;
    apb.mon.ap.connect(pred.bus_in);
  endfunction
endclass

[UVM] [RAL] explicit prediction flow

  write/read issued
      |
      v
  monitor captures actual bus transaction
      |
      v
  predictor + bus2reg decode operation
      |
      v
  mirror update occurs from observed behavior

  Benefit: mirror follows what bus did, not just intent

• Explicit prediction is safer in multi-master and side-effect-heavy designs.

• Monitor quality directly impacts mirror integrity.

• bus2reg should decode exactly what monitor records, not what sequence intended.

bus2reg implementation patterns and checks

A good bus2reg handles cast safety, read/write extraction, status derivation, and optional byte-enable mapping. Defensive checks here reduce hours of mirror-debug churn.

virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
  apb_item tr;
  if (!$cast(tr, bus_item)) begin
    `uvm_error("RAL_ADAPT", $sformatf("bus2reg cast failed: got %s", bus_item.get_type_name()))
    rw.status = UVM_NOT_OK;
    return;
  end

  rw.kind = tr.write ? UVM_WRITE : UVM_READ;
  rw.addr = tr.addr;

  if (tr.write)
    rw.data = tr.wdata;
  else
    rw.data = tr.rdata;

  rw.byte_en = tr.strb;
  rw.status  = tr.slv_err ? UVM_NOT_OK : UVM_IS_OK;

  if (rw.status != UVM_IS_OK) begin
    `uvm_warning(
      "RAL_ADAPT",
      $sformatf("BUS ERR kind=%s addr=0x%0h", (rw.kind==UVM_WRITE)?"WRITE":"READ", rw.addr)
    )
  end
endfunction

[BUS] bus2reg decode matrix

  write item:
    rw.kind = UVM_WRITE
    rw.data = observed write payload

  read item:
    rw.kind = UVM_READ
    rw.data = observed return data

  protocol error:
    rw.status = UVM_NOT_OK

[RAL] mirror drift triage starting points

  If mirror != DUT:
    1) verify monitor saw the transaction
    2) verify bus2reg decoded addr/data correctly
    3) verify rw.status was UVM_IS_OK
    4) verify map addressing matches monitor address space

Key takeaways

• bus2reg is the prediction decoder and mirror truth source.

• Cast checks and status mapping must be explicit and defensive.

• Disable auto_predict when using predictor path for robust synchronization.

• Most mirror drift bugs trace to monitor decode or bus2reg mapping errors.

Common pitfalls

• Filling rw.data from write payload during reads by mistake.

• Ignoring bus error indicators, causing false mirror confidence.

• Using auto_predict and explicit predictor simultaneously without intent.

• Assuming bus_item types never vary; cast failures happen in real benches.