Part 9 · Register Model (RAL) · Intermediate

mirror(UVM_CHECK) Compare Workflow

How mirror(UVM_CHECK) performs read-and-compare, what passes/failures actually mean, and how to place checks in stable verification flows.

What mirror(UVM_CHECK) does

Calling mirror(status, UVM_CHECK, path, map, parent) triggers a DUT read through the selected path and compares observed value against mirrored expectation, with standardized UVM diagnostics on mismatch.

diagram
[RAL] mirror(UVM_CHECK) execution model

  Step 1:
    expected = current mirrored value

  Step 2:
    perform read via selected path (frontdoor/backdoor)

  Step 3:
    compare observed vs expected (policy-aware masks may apply)

  Step 4:
    report pass/fail using UVM register reporting

  Step 5:
    update mirror with observed value (successful read path)

  Consequence:
    a failed check may still refresh mirror for subsequent operations.
diagram
[CHECK] interpreting failures

  mismatch + stable predictor:
    likely DUT discrepancy or unmodeled side effect

  mismatch + missing/stale predictor:
    likely false failure (expected baseline stale)

  repeated mismatch on same bit:
    check access policy, adapter bit-lane mapping, endianness, and volatile setting

Canonical usage pattern

Use mirror checks at meaningful checkpoints: post-reset, post-configuration, and post-operation boundaries. Avoid over-checking mid-transaction where hardware state is intentionally transient.

systemverilog
task checkpoint_mirror_checks(my_reg_block ral, uvm_component parent);
  uvm_status_e status;

  // After reset sequence and predictor stabilization.
  ral.ctrl.mirror(status, UVM_CHECK, UVM_FRONTDOOR, .parent(parent));
  if (status != UVM_IS_OK)
    `uvm_error("MIRROR", "ctrl mirror check failed after reset")

  // After configuration commit.
  ral.mode.mirror(status, UVM_CHECK, UVM_FRONTDOOR, .parent(parent));
  if (status != UVM_IS_OK)
    `uvm_error("MIRROR", "mode mirror check failed after cfg")
endtask

When UVM_NO_CHECK is useful

  • Resynchronizing mirror after known external writes without asserting mismatch.

  • Bringing model back to observed state before a strict compare phase.

  • Debug runs where first goal is localization, not pass/fail gating.

systemverilog
// Resync mirror without failing test
ral.status.mirror(status, UVM_NO_CHECK, UVM_FRONTDOOR, .parent(this));
// Later strict check
ral.status.mirror(status, UVM_CHECK, UVM_FRONTDOOR, .parent(this));

Path choice and compare trust

Frontdoor mirror checks validate bus path plus register content. Backdoor checks validate direct storage value but bypass protocol logic. Choose based on verification objective.

diagram
[UVM] compare objective matrix

  Path            Validates                               Typical use
  ───────────────────────────────────────────────────────────────────────────────
  UVM_FRONTDOOR   bus decode + protocol + register state  integration and sign-off
  UVM_BACKDOOR    raw RTL register storage                fast debug and setup validation

  Guidance:
    - for bug triage: run backdoor check to isolate data vs bus path issues
    - for coverage closure: retain frontdoor checks
systemverilog
task dual_path_diagnose(my_reg_block ral, uvm_component parent);
  uvm_status_e s_fd, s_bd;

  ral.ctrl.mirror(s_fd, UVM_CHECK, UVM_FRONTDOOR, .parent(parent));
  ral.ctrl.mirror(s_bd, UVM_CHECK, UVM_BACKDOOR, .parent(parent));

  if ((s_fd != UVM_IS_OK) && (s_bd == UVM_IS_OK))
    `uvm_warning("MIRROR", "frontdoor-only mismatch suggests bus path issue")
endtask

Designing robust compare checkpoints

Mirror checks are most effective when surrounding infrastructure is deterministic: predictor connected, objections stable, scoreboard drains complete, and no concurrent unknown writers.

  1. Ensure predictor received and applied all relevant monitor transactions.

  2. Avoid mirror checks inside windows where other masters actively modify same register.

  3. Use path-specific checks intentionally (frontdoor for proof, backdoor for triage).

  4. Capture desired and mirrored values on failure for immediate diagnosis.

  5. Pair compare failures with adapter/map context in logs to cut debug time.

diagram
[CHECK] mirror failure triage packet (collect on first mismatch)

  - register full name
  - path used (frontdoor/backdoor)
  - map name
  - mirrored before check
  - observed read value
  - desired value
  - last predictor transaction for this address
  - access policy metadata (RW/W1C/RC/volatile)

Key takeaways

  • mirror(UVM_CHECK) is a read-and-compare against mirrored baseline.

  • The check is only as trustworthy as mirror freshness and policy modeling.

  • Frontdoor and backdoor checks answer different validation questions.

  • Use consistent checkpoint placement for deterministic regressions.

Common pitfalls

  • Running strict checks while concurrent writers legitimately change the same CSR.

  • Treating first mismatch as DUT bug without verifying predictor freshness.

  • Using backdoor-only checks for sign-off of bus-facing behavior.