uvm_reg_hw_reset_seq Deep Dive

Why start with uvm_reg_hw_reset_seq

The built-in uvm_reg_hw_reset_seq is usually the highest-value first RAL test. It validates map traversal, address accessibility, and reset values with minimal custom code.

It quickly answers: does the post-reset DUT state match model expectations? If not, logs point directly to register/field mismatches, giving an early signal on both model and RTL quality.

[UVM][RAL] hw_reset_seq high-level flow

  sequence starts
    ▼
  walk model registers in map
    ▼
  read each register via selected path/map
    ▼
  compare observed against modeled reset values
    ▼
  report mismatches with register context

[TEST] bring-up order recommendation

  1) reset DUT and clocks stable
  2) run hw_reset_seq
  3) fix model/map/reset mismatches
  4) run bit_bash/access seqs
  5) move to scenario-level register tests

• Run this sequence early in block and subsystem bring-up.

• Failures often expose foundational issues before complex tests begin.

• Keep logs clean and deterministic to accelerate root-cause loops.

Minimal runnable test setup

The sequence needs a built and connected model. For frontdoor usage, map sequencer/adapter and predictor wiring must already be valid in env.

class ral_hw_reset_test extends uvm_test;
  `uvm_component_utils(ral_hw_reset_test)
  reg_env env;

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    env = reg_env::type_id::create("env", this);
  endfunction

  task run_phase(uvm_phase phase);
    uvm_reg_hw_reset_seq seq;

    phase.raise_objection(this);

    // Ensure DUT reset is applied and released before sequence
    env.reset_dut();

    seq = uvm_reg_hw_reset_seq::type_id::create("seq");
    seq.model = env.reg_model;
    seq.start(null); // uses map sequencer setup in model/env

    phase.drop_objection(this);
  endtask
endclass

[UVM] prerequisites before seq.start

  - reg_model built and lock_model called
  - default_map set with sequencer+adapter (frontdoor)
  - reset sequence completed in DUT
  - any excluded regs/fields configured

• Use one canonical env wiring path so all reset tests share setup.

• Keep reset application explicit in run_phase, not implicit side effects.

• Log reset completion time to correlate with first register read.

Selective exclusion and customization patterns

Not all registers should be checked blindly: write-only command regs, undefined-reset debug regs, or hardware dynamic status may require exclusions.

class my_hw_reset_seq extends uvm_reg_hw_reset_seq;
  `uvm_object_utils(my_hw_reset_seq)

  // Example helper to skip known non-deterministic registers
  virtual function bit is_reg_excluded(uvm_reg rg);
    string n = rg.get_full_name();
    if (n.tolower().find("dbg_nonce") != -1) return 1;
    if (n.tolower().find("cmd_kick")  != -1) return 1; // WO command register
    return 0;
  endfunction

  virtual task body();
    uvm_reg regs[$];
    if (model == null)
      `uvm_fatal("RSTSEQ", "model is null")

    model.get_registers(regs);
    foreach (regs[i]) begin
      if (is_reg_excluded(regs[i])) begin
        `uvm_info("RSTSEQ", {"Skipping ", regs[i].get_full_name()}, UVM_LOW)
        continue;
      end
      // In real projects, call base behavior or custom check helper here
      // based on your environment's sequence customization style.
    end
  endtask
endclass

[RAL] exclusion policy guidance

  Include by default:
    deterministic reset, software-readable fields

  Exclude explicitly:
    WO command registers
    undefined-reset debug entropy fields
    rapidly changing autonomous counters (unless sampled deterministically)

  Always log exclusions to keep test intent auditable.

• Exclusions must be spec-justified and documented, never ad hoc.

• Keep skip lists small and reviewable to avoid hiding real bugs.

• Prefer field-level masking over full-register exclusion when possible.

Interpreting reset sequence failures

A reset mismatch report is a symptom, not a root cause. Fast triage means classifying failure type immediately.

[UVM][RAL] hw_reset_seq failure classifier

  Type 1: all registers fail
    likely map/adapter/path/reset-order issue

  Type 2: one register fails consistently
    likely model reset mismatch or RTL bug in that register

  Type 3: one field fails within mixed register
    likely field configure/reset metadata issue

  Type 4: intermittent volatile status mismatch
    likely check timing/probe window issue

task triage_hw_reset_fail(string reg_name, uvm_reg_data_t exp, uvm_reg_data_t got);
  `uvm_info("TRIAGE",
    $sformatf("reg=%s exp=0x%0h got=0x%0h xor=0x%0h", reg_name, exp, got, (exp ^ got)),
    UVM_LOW)

  // Example: bit-localization helper
  for (int b = 0; b < 32; b++) begin
    if (exp[b] !== got[b])
      `uvm_info("TRIAGE", $sformatf("bit mismatch at %0d", b), UVM_HIGH)
  end
endtask

• Start with scope classification: global, per-register, or per-field.

• Use xor bit localization to map mismatch directly to field definitions.

• Confirm reset sequence ordering before deep model surgery.

Frontdoor vs backdoor reset checks

Frontdoor reset checks validate bus path + reset state. Backdoor checks validate storage state quickly. Both are useful at different stages.

[RAL][RESET] access path tradeoff

  FRONTDOOR:
    + validates bus decode and protocol path
    - slower

  BACKDOOR:
    + very fast, great for early triage
    - bypasses bus path validation

  Typical flow:
    backdoor debug -> frontdoor signoff

// Optional quick cross-check snippet
task reset_cross_check(my_reg_block ral, uvm_reg rg);
  uvm_status_e status;
  uvm_reg_data_t fd, bd;
  rg.read(status, fd, UVM_FRONTDOOR, ral.default_map, this);
  rg.read(status, bd, UVM_BACKDOOR,  ral.default_map, this);
  if (fd !== bd)
    `uvm_warning("RSTPATH", $sformatf("FD/BD mismatch on %s", rg.get_full_name()))
endtask

Key takeaways

• uvm_reg_hw_reset_seq is the fastest path to high-signal RAL bring-up feedback.

• Good setup requires model, map, adapter, reset ordering, and documented exclusions.

• Failure triage should classify mismatch scope before deep investigation.

• Use backdoor for rapid diagnosis and frontdoor for integration confidence.

Common pitfalls

• Running hw_reset_seq before DUT reset completes.

• Silent exclusions that hide real reset design defects.

• Treating every mismatch as RTL bug without validating model metadata.

• Backdoor-only reset signoff that misses bus-path integration issues.