Part 11 · Senior Prep · Intermediate

Block to SoC Interview Q&A: Reuse and Passive Flip

Model answers on inheriting block TB at chip, passive-agent patterns, virtual sequences, integration scoreboards, and VIP API boundaries.

Block → chip transition questions

Q: You inherit a block TB going to chip — what changes?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Block TB → chip integration — your plan?

A:
  MECHANISM:  Reuse agents passive where RTL drives; add chip scoreboard and
              software-like virtual sequences; distribute config via config_db.
  MOTIVATION:  Same VIP must serve block sign-off and chip integration without
              rewrite — architecture is economics of reuse.
  PLAN:       1) Audit active agents — flip passive on integrated interfaces.
              2) Add end-to-end scoreboard path across subtrees.
              3) Virtual sequencer for cross-cluster scenarios.
              4) Merge coverage from block + chip regressions with plan map.
  PITFALL:    Leaving block active master on bus now driven by CPU RTL.
  EXAMPLE:    PCIe EP agent passive at chip; root complex RTL drives; monitor
              feeds chip-level fabric scoreboard.

Q: How do you structure a reusable VIP for block and chip?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Reusable VIP API?

A:
  MECHANISM:  Config object + sequence library + analysis port — documented,
              stable; internals private.
  MOTIVATION:  Integrators should not edit VIP internals per project.
  API:        cfg (is_active, timing knobs), seq_lib (legal protocol scenarios),
              mon.ap (observed txn stream), optional coverage enable flag.
  PITFALL:    Exposing driver handles — integrators couple to implementation.
  EXAMPLE:    axi_vip_pkg exports axi_agent, axi_config, axi_seq_lib::* — no
              direct drv field access in integration guide.

systemverilog

class axi_cfg extends uvm_object;
  `uvm_object_utils(axi_cfg)
  uvm_active_passive_enum is_active = UVM_ACTIVE;
  string if_name = "axi_if0";
  bit enable_coverage = 1;
  int unsigned max_outstanding = 16;
endclass

// chip integrator sets passive — same agent class
initial begin
  axi_cfg chip_cfg = axi_cfg::type_id::create("chip_cfg");
  chip_cfg.is_active = UVM_PASSIVE;
  uvm_config_db#(axi_cfg)::set(null, "uvm_test_top.env.axi_agt", "cfg", chip_cfg);
end

Q: Active at block, passive at chip — walk through connect_phase

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Passive flip — what wires change?

A:
  MECHANISM:  Passive agent builds monitor only; no drv/sqr; mon.ap still fans
              to scoreboard and coverage.
  MOTIVATION:  RTL (CPU, fabric) drives pins — TB must observe, not compete.
  CONNECT:    mon.ap → chip_sb.act_export; mon.ap → cov_subscriber; no
              seq_item_port connection because no driver exists.
  PITFALL:    Passive agent still running master sequences — protocol collision.
  EXAMPLE:    APB passive at chip: monitor samples PSEL/PENABLE; CPU RTL drives.

Key takeaways

Chip integration = passive flip + virtual seq + end-to-end checking.
VIP API = config + seq library + analysis port — hide internals.
Sketch reuse ladder when asked architecture scenarios.

Common pitfalls

Rebuilding agents per level instead of one configurable VIP.
Chip scoreboard that only checks local block traffic.

Integration scoreboard and virtual sequences

Q: Block scoreboard vs chip scoreboard — who owns what?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Block SB vs chip SB?

A:
  MECHANISM:  Block SB checks protocol + local algorithm inside block boundary.
              Chip SB checks end-to-end paths across blocks (DMA, routing, coherency).
  MOTIVATION:  Block sign-off does not prove system paths — chip layer adds scope.
  WHEN:       Keep block SB in block env for block regressions; add chip SB that
              subscribes to multiple passive monitor streams at SoC.
  PITFALL:    Disabling block SB at chip and losing block-level corner checks.
  EXAMPLE:    Block AES SB checks encrypt output; chip SB checks DMA wrote ciphertext
              to correct memory region visible to CPU monitor.

Q: How do virtual sequences coordinate multi-agent chip scenarios?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Chip-level virtual sequence?

A:
  MECHANISM:  Virtual sequencer holds handles to leaf sequencers; virtual seq
              starts sub-sequences on each domain in legal order.
  MOTIVATION:  SW-like bring-up (configure clocks, load image, kick DMA) spans
              multiple interfaces — one seq coordinates without env coupling.
  WHEN:       Chip scenarios crossing APB cfg + AXI traffic + interrupt wait.
  PITFALL:    Virtual seq poking driver fields — must use published leaf sequencers.
  EXAMPLE:    vseq: APB programs PLL → AXI loads firmware → wait IRQ → AXI peek status.

systemverilog

class chip_virtual_sequencer extends uvm_sequencer;
  `uvm_component_utils(chip_virtual_sequencer)
  apb_sequencer apb_sqr;
  axi_sequencer axi_sqr;
endclass

class boot_vseq extends uvm_sequence;
  `uvm_object_utils(boot_vseq)
  `uvm_declare_p_sequencer(chip_virtual_sequencer)

  task body();
    apb_cfg_seq apb_seq = apb_cfg_seq::type_id::create("apb_seq");
    axi_load_seq axi_seq = axi_load_seq::type_id::create("axi_seq");
    apb_seq.start(p_sequencer.apb_sqr);
    axi_seq.start(p_sequencer.axi_sqr);
  endtask
endclass

diagram

[INT][SENIOR][UVM] whiteboard: chip check pipeline

  CPU RTL drives AXI ──► axi_mon.ap ──┬──► chip_scoreboard (actual)
  DMA RTL drives AXI ──► dma_mon.ap ──┤
  APB cfg traffic    ──► apb_mon.ap ──┴──► ref_model ──► chip_sb (expected)

  Label: passive monitors only on driven interfaces
         block SB may run inside block sub-env for block regressions

Key takeaways

Block SB = local correctness; chip SB = system path correctness.
Virtual seq coordinates leaf sequencers — never driver internals.
Whiteboard check pipeline faster than verbal hand-waving.

Common pitfalls

Virtual sequencer without handles to all required leaf sequencers.
Chip TB with no scenario library — only directed one-offs.

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