Coding & Whiteboard Interview Hub

Whiteboard rounds test implementation fluency

Interviewers ask you to sketch and narrate working SystemVerilog — scoreboard with FIFO ordering, monitor packing, reg adapter mapping, sequence body, config_db paths. Talk mechanism while drawing; cite pitfalls unprompted.

Sub-lessons in this topic

1. scoreboard-fifo-qa — ordered compare, out-of-order buses, overflow.

2. monitor-reconstruct-qa — beat packing, byte enables, protocol state.

3. adapter-reg2bus-qa — reg2bus, bus2reg, field masks, byte order.

4. sequence-basic-qa — item, body, objections, handshake.

5. config-db-wiring-qa — set/get paths, vif push, cfg distribution.

6. whiteboard-delivery-tips — pacing, structure, common mistakes.

[INT][SENIOR][UVM] whiteboard delivery chain

1. DECLARE    interfaces / types / ports you need
2. SKELETON   class extends + utils macro + key methods
3. MECHANISM  fill one critical method while narrating
4. PITFALL    name one bug juniors make on this pattern
5. TEST       how you would smoke-test the component

[INT][SENIOR][UVM] daily drill rotation

  Mon: scoreboard FIFO + compare
  Tue: monitor reconstruct one protocol beat
  Wed: reg adapter reg2bus/bus2reg
  Thu: sequence + driver handshake
  Fri: config_db set/get from top to agent

Key takeaways

• Sketch class skeleton first — then fill one method deeply.

• Narrate pitfall unprompted — senior signal on whiteboard rounds.

• Every drill ties to a smoke test — shows closure mindset.

Common pitfalls

• Writing syntax-perfect code silently — narrate mechanism.

• Starting with details before class boundary — confuses interviewer.

Preparation checklist

• Memorize uvm_component_utils and uvm_object_utils placement.

• Know seq_item_port get_next_item / item_done / put handshake by heart.

• Practice reg2bus direction — reg item to bus txn, not reversed.

• config_db: set from top with null, get in agent build_phase.