Part 11 · Senior Prep · Intermediate

RAL Adapter reg2bus Whiteboard Q&A

Model answers on uvm_reg_adapter reg2bus/bus2reg, byte enables, bus direction, predictor hookup, and frontdoor path whiteboard.

Adapter mechanism questions

Q: Whiteboard reg2bus and bus2reg — what each does

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: reg2bus vs bus2reg?

A:
  MECHANISM:  reg2bus converts uvm_reg_bus_op (from reg.write) to bus-specific txn
              for sequencer. bus2reg converts observed bus txn back to reg_bus_op
              for predictor/mirror update.
  MOTIVATION:  RAL is bus-agnostic — adapter is the only bus-specific layer.
  PITFALL:    Swapping directions — classic whiteboard fail.
  EXAMPLE:    reg.write → reg2bus → apb_txn → sequencer → driver → DUT.

systemverilog

class apb_reg_adapter extends uvm_reg_adapter;
  `uvm_object_utils(apb_reg_adapter)

  function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
    apb_txn t = apb_txn::type_id::create("t");
    t.addr  = rw.addr;
    t.write = (rw.kind == UVM_WRITE);
    t.data  = rw.data;
    return t;
  endfunction

  function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
    apb_txn t;
    if (!$cast(t, bus_item)) `uvm_fatal("ADP", "cast fail")
    rw.kind = t.write ? UVM_WRITE : UVM_READ;
    rw.addr = t.addr;
    rw.data = t.data;
    rw.status = t.slverr ? UVM_NOT_OK : UVM_IS_OK;
  endfunction
endclass

Q: Where does adapter plug into env?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Adapter integration?

A:
  MECHANISM:  reg_model.default_map.set_sequencer(agt.sqr, adapter);
              predictor maps bus mon → bus2reg → mirror.
  MOTIVATION:  Frontdoor path needs sequencer + adapter pair registered on map.
  CONNECT:    mon.ap → predictor.bus_in; predictor.map = reg_model.default_map.
  PITFALL:    Adapter set but sequencer null — reg.write hangs in frontdoor.

systemverilog

function void connect_phase(uvm_phase phase);
  super.connect_phase(phase);
  apb_reg_adapter adp = apb_reg_adapter::type_id::create("adp");
  reg_model.default_map.set_sequencer(agt.sqr, adp);
  predictor.map = reg_model.default_map;
  predictor.adapter = adp;
  agt.mon.ap.connect(predictor.bus_in);
endfunction

Key takeaways

reg2bus: RAL → bus txn; bus2reg: bus txn → RAL — do not swap.
set_sequencer(sqr, adapter) on default_map — frontdoor requirement.
Predictor: mon.ap → bus_in + adapter + map.

Common pitfalls

Forgetting supports_byte_enable on adapter — sub-word writes break.
bus2reg status always UVM_IS_OK — slverr paths never propagate.

Field masks and byte order

Q: Sub-word write — how does adapter handle byte_en?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Byte enable handling?

A:
  MECHANISM:  adapter provides byte_en from reg_bus_op; driver maps to wstrb/pstrb.
  MOTIVATION:  32-bit reg in 64-bit bus needs lane selection — field access supplies mask.
  PITFALL:    Full-width write always — corrupts adjacent fields in same register.
  EXAMPLE:    STATUS field write sets byte_en=4'b0011 — lower half only.

Q: Endianness and address alignment in adapter

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Endian / alignment?

A:
  MECHANISM:  reg offset from map + bus width determines lane shift in data.
  MOTIVATION:  APB 32-bit at offset 4 in 64-bit word — data in upper half.
  PITFALL:    Using byte address as word index without >>2 — classic adapter bug.
  EXAMPLE:    addr=0x4 on 64-bit bus → data << 32 in reg2bus mapping.

systemverilog

function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
  apb_txn t = apb_txn::type_id::create("t");
  int unsigned lane = (rw.addr % (DATA_WIDTH/8));
  t.addr = rw.addr;
  t.data = rw.data >> (lane * 8);  // simplify — interview shows awareness
  t.strb = rw.byte_en << lane;
  return t;
endfunction

Q: Whiteboard full frontdoor path

diagram

[INT][SENIOR][UVM] whiteboard frontdoor

  seq.reg.write(status, val, .parent(this))
       → default_map → reg2bus → apb_txn
       → sequencer → driver → DUT pins
  DUT → monitor → bus2reg → predictor → mirror update

  Narrate each arrow — common 5-minute interview drill

Key takeaways

byte_en / strb mapping — required for sub-word RAL writes.
Address lane shift for wide bus — show >>2 and lane awareness.
Draw full frontdoor path — seq to mirror in one diagram.

Common pitfalls

backdoor and frontdoor confused on whiteboard — separate paths.
predictor not connected — mirror stale after frontdoor traffic.

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