Part 11 · Senior Prep · Intermediate
Monitor Reconstruct Whiteboard Q&A
Model answers on rebuilding protocol transactions from pin-level activity, beat packing, byte enables, and monitor vs driver sampling for coverage.
Monitor structure questions
Q: Whiteboard a monitor class skeleton
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Monitor skeleton?
A:
MECHANISM: Virtual interface + analysis port + run_phase forever loop sampling pins.
Assemble txn item field-by-field; write to ap when txn complete.
MOTIVATION: Monitor is DUT-observable truth — coverage and scoreboard source.
PITFALL: Monitor driving pins — role confusion with driver.
EXAMPLE: APB monitor: wait PSEL, capture addr/write/data, wait PREADY, emit txn.systemverilog
class apb_monitor extends uvm_monitor;
`uvm_component_utils(apb_monitor)
virtual apb_if vif;
uvm_analysis_port #(apb_txn) ap;
apb_cfg cfg;
function void build_phase(uvm_phase phase);
super.build_phase(phase);
ap = new("ap", this);
if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))
`uvm_fatal("MON", "no vif")
uvm_config_db#(apb_cfg)::get(this, "", "cfg", cfg);
endfunction
task run_phase(uvm_phase phase);
apb_txn t;
forever begin
@(posedge vif.pclk);
if (vif.psel && vif.penable && vif.pready) begin
t = apb_txn::type_id::create("t");
t.addr = vif.paddr;
t.write = vif.pwrite;
t.data = vif.prdata;
t.slverr = vif.pslverr;
ap.write(t);
end
end
endtask
endclassQ: Reconstruct wide AXI beat from W channel beats
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: AXI W beat packing?
A:
MECHANISM: Accumulate wdata into txn.data[] using wstrb for byte lanes; wlast
marks txn complete → ap.write.
MOTIVATION: Scoreboard compares full beat — not individual W cycles in isolation.
PITFALL: Ignoring wstrb — partial writes compare wrong on wide bus.
EXAMPLE: 64-bit bus, wstrb=8'h0F — lower 32 bits valid only.systemverilog
task collect_write_data(axi_txn t);
bit [7:0] wdata;
bit [7:0] wstrb;
@(posedge vif.aclk);
wdata = vif.wdata;
wstrb = vif.wstrb;
for (int i = 0; i < 8; i++)
if (wstrb[i]) t.data[i*8 +: 8] = wdata[i*8 +: 8];
if (vif.wlast) ap.write(t);
endtaskKey takeaways
Monitor = vif + ap + run_phase sampling loop — never drives pins.
Pack multi-beat writes with wstrb awareness — whiteboard detail interviewers want.
Emit txn on transaction complete (wlast, rlast) — not every beat.
Common pitfalls
Coverage sampled on driver — cite monitor-only rule in interview.
Missing slverr/rresp in txn — scoreboard cannot check error paths.
Protocol state and check hooks
Q: How does monitor track protocol state machine?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Monitor FSM?
A:
MECHANISM: Enum state variable updated each cycle; illegal transitions → uvm_error.
MOTIVATION: Protocol checker embedded in monitor — no separate passive checker needed for simple rules.
WHEN: APB, SPI, simple FIFO protocols on whiteboard.
PITFALL: FSM in driver only — passive chip config has no driver.
EXAMPLE: AXI AR valid held without ready 512 cycles → protocol violation report.Q: Monitor coverage subscriber — where do you hook?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Coverage hook point?
A:
MECHANISM: cov_subscriber extends uvm_subscriber #(txn); connect mon.ap to it.
MOTIVATION: Sample DUT-visible completed txn — same stream as scoreboard actual.
PITFALL: Separate covergroup in driver — driver stream ≠ DUT reality.
EXAMPLE: mon.ap → cov_sub.write → cg.sample(t) on t.rsp_phase.systemverilog
class axi_cov_subscriber extends uvm_subscriber #(axi_txn);
`uvm_component_utils(axi_cov_subscriber)
axi_cov cg;
function void write(axi_txn t);
if (t.rsp_phase) cg.sample(t);
endfunction
endclassQ: Passive monitor at chip — any run_phase difference?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Passive monitor at chip?
A:
MECHANISM: Same reconstruct logic — samples pins RTL drives; no seq_item_port.
MOTIVATION: Chip TB observes CPU/RTL traffic; monitor is primary stimulus observer.
CONNECT: mon.ap → chip_sb + cov only — no driver path exists.
PITFALL: Disabling monitor assertions because 'chip is passive' — wrong.Key takeaways
Monitor FSM catches protocol violations — required for passive chip agents.
Coverage subscriber on mon.ap — rsp_phase sample gate.
Passive monitor code same as active — only driver/seq absent.
Common pitfalls
Monitor task without reset wait — samples X during reset.
Illegal transition check missing — only data capture, no protocol guard.