Part 11 · Senior Prep · Intermediate
Scoreboard FIFO Whiteboard Q&A
Model answers and SystemVerilog sketches for ordered and out-of-order scoreboards, FIFO depth, compare granularity, and mismatch debug.
Scoreboard architecture questions
Q: Whiteboard a scoreboard with expected and actual FIFOs
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Scoreboard FIFO whiteboard?
A:
MECHANISM: Two analysis imports — expected from ref_model, actual from monitor.
On each actual, pop/compare against expected FIFO head (or search if OOO).
MOTIVATION: Decouple predict timing from DUT latency — FIFO absorbs pipeline delay.
WHEN: Any bus with variable response latency (AXI, PCIe, network).
PITFALL: Single queue without direction label — cannot tell exp vs act mismatch.
EXAMPLE: AXI write addr on act, ref_model pushes exp resp when B channel arrives.systemverilog
class axi_scoreboard extends uvm_scoreboard;
`uvm_component_utils(axi_scoreboard)
uvm_analysis_imp_exp #(axi_txn, axi_scoreboard) exp_imp;
uvm_analysis_imp_act #(axi_txn, axi_scoreboard) act_imp;
axi_txn exp_q[$], act_q[$];
function new(string name, uvm_component parent);
super.new(name, parent);
exp_imp = new("exp_imp", this);
act_imp = new("act_imp", this);
endfunction
function void write_exp(axi_txn t);
if (t.rsp_phase) exp_q.push_back(t);
endfunction
function void write_act(axi_txn t);
if (t.rsp_phase) begin
act_q.push_back(t);
compare_head();
end
endfunction
function void compare_head();
axi_txn exp, act;
if (exp_q.size() == 0 || act_q.size() == 0) return;
exp = exp_q.pop_front();
act = act_q.pop_front();
if (exp.data !== act.data)
`uvm_error("SCB", $sformatf("mismatch exp=%0h act=%0h", exp.data, act.data))
endfunction
endclassQ: Out-of-order responses — how does scoreboard change?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: OOO scoreboard?
A:
MECHANISM: Key compare by transaction ID — associative array id → expected txn.
On actual, lookup id, compare fields, delete entry.
MOTIVATION: AXI outstanding writes complete in arbitrary order.
PITFALL: FIFO head compare on OOO bus — false mismatches every other txn.
EXAMPLE: exp_map[t.id] = t on predict; act arrives with id=7 → lookup exp_map[7].systemverilog
axi_txn exp_map[int unsigned]; // keyed by txn id
function void write_exp(axi_txn t);
if (t.rsp_phase) exp_map[t.id] = t;
endfunction
function void write_act(axi_txn t);
axi_txn exp;
if (!exp_map.exists(t.id))
`uvm_error("SCB", $sformatf("unexpected id=%0d", t.id))
else begin
exp = exp_map[t.id];
if (exp.data !== t.data) `uvm_error("SCB", "data mismatch")
exp_map.delete(t.id);
end
endfunctionKey takeaways
In-order: dual FIFO head compare on response phase.
Out-of-order: associative array keyed by txn ID.
Compare on response/rsp_phase — not address phase alone.
Common pitfalls
FIFO compare on request beat when response is OOO — wrong granularity.
No check for orphan expected entries at end of test — report_phase sweep.
FIFO depth and end-of-test
Q: How do you size scoreboard FIFO depth?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: FIFO depth sizing?
A:
MECHANISM: Depth ≥ max outstanding transactions × pipeline stages.
MOTIVATION: Overflow drops compare pairs — silent verification hole.
WHEN: Parameterize depth from cfg.max_outstanding — interviewers want link.
PITFALL: Fixed depth 16 on bus with 64 outstanding — overflow drops txns.
EXAMPLE: AXI max_outstanding=32 → FIFO depth 64 with margin for ref_model delay.Q: report_phase — what scoreboard checks do you add?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: End-of-test scoreboard?
A:
MECHANISM: report_phase sweeps orphan exp_q or exp_map entries.
MOTIVATION: DUT dropped response — FIFO would hide missing beats without sweep.
CODE: if (exp_map.num() != 0) uvm_error orphan expected count.
PITFALL: Only checking UVM_ERROR count — orphans never compared if act never arrived.systemverilog
function void report_phase(uvm_phase phase);
super.report_phase(phase);
if (exp_q.size() > 0)
`uvm_error("SCB", $sformatf("%0d orphan expected", exp_q.size()))
if (act_q.size() > 0)
`uvm_error("SCB", $sformatf("%0d orphan actual", act_q.size()))
endfunctionQ: Whiteboard monitor → scoreboard connection
diagram
[INT][SENIOR][UVM] whiteboard wiring
env.connect_phase:
agt.mon.ap.connect(scb.act_export);
ref_model.ap.connect(scb.exp_export);
Narrate: analysis_port → analysis_export → write_act/write_exp
TLM FIFO implicit between port and exportKey takeaways
Size FIFO from cfg.max_outstanding — parameterize, do not hardcode.
report_phase orphan sweep — mandatory for complete checking.
Draw connect_phase wiring — common whiteboard follow-up.
Common pitfalls
compare without rsp_phase filter — double-count address and response.
Orphan sweep missing on OOO map — leaked IDs hide DUT drops.