Part 11 · Senior Prep · Intermediate
Basic Sequence Whiteboard Q&A
Model answers on uvm_sequence_item, sequence body, objections, driver handshake, and virtual sequence coordination sketches.
Sequence and item questions
Q: Whiteboard sequence_item + sequence + driver handshake
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Sequence handshake whiteboard?
A:
MECHANISM: seq.start(sqr) → body() → start_item/finish_item or `uvm_do
→ driver get_next_item → drive pins → item_done.
MOTIVATION: Pull model decouples sequence from pin wiggle — reuse sequences.
PITFALL: item_done before drive completes — race on next item.
EXAMPLE: apb_write_seq: randomize addr/data, `uvm_do_with(req, {addr inside {[0:255]};})systemverilog
class apb_txn extends uvm_sequence_item;
`uvm_object_utils(apb_txn)
rand bit [31:0] addr, data;
rand bit write;
constraint c_addr { addr[1:0] == 0; }
endclass
class apb_write_seq extends uvm_sequence #(apb_txn);
`uvm_object_utils(apb_write_seq)
rand int unsigned n_txns = 10;
task body();
repeat (n_txns) begin
`uvm_do_with(req, { write == 1; })
end
endtask
endclasssystemverilog
class apb_driver extends uvm_driver #(apb_txn);
virtual apb_if vif;
task run_phase(uvm_phase phase);
forever begin
seq_item_port.get_next_item(req);
@(posedge vif.pclk);
vif.psel <= 1'b1;
vif.pwrite <= req.write;
vif.paddr <= req.addr;
vif.pwdata <= req.data;
wait (vif.pready);
seq_item_port.item_done();
end
endtask
endclassQ: Where do objections go — test or sequence?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Objection placement?
A:
MECHANISM: raise/drop in run_phase of test OR sequence that owns full scenario.
MOTIVATION: run_phase ends when all objections dropped — must cover driver drain.
WHEN: Test raises for smoke; long vseq raises internally for multi-branch.
PITFALL: raise in build_phase — invalid; drop before driver item_done — early end.
EXAMPLE: test run_phase: raise → vseq.start → drop — simplest pattern.Key takeaways
Pull model: get_next_item → drive → item_done — narrate in order.
Constraints on item — sequence randomizes per uvm_do macro.
Objections in run_phase task — test or owning sequence.
Common pitfalls
finish_item without waiting response on bus — next item collides.
Fork in sequence without join before drop_objection — hang.
Virtual sequences and arbitration
Q: Sketch virtual sequence starting two leaf sequences
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Virtual seq whiteboard?
A:
MECHANISM: vseq on virtual_sqr; p_sequencer holds apb_sqr and axi_sqr handles.
body: create leaf seqs, start on respective sequencers — fork/join as needed.
MOTIVATION: Chip scenarios span interfaces — one seq coordinates without env coupling.
PITFALL: Virtual seq calling driver directly — bypasses sequencer arbitration.
EXAMPLE: cfg on APB then bulk on AXI — sequential start, not parallel unless intended.systemverilog
class chip_vseq extends uvm_sequence;
`uvm_object_utils(chip_vseq)
`uvm_declare_p_sequencer(chip_virtual_sequencer)
task body();
apb_cfg_seq a_seq = apb_cfg_seq::type_id::create("a_seq");
axi_burst_seq x_seq = axi_burst_seq::type_id::create("x_seq");
a_seq.start(p_sequencer.apb_sqr);
x_seq.start(p_sequencer.axi_sqr);
endtask
endclassQ: sequencer arbitration — SEQ_ARB_STRICT_FIFO meaning?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Arbitration mode?
A:
MECHANISM: STRICT_FIFO — sequences complete in start order; one at a time.
MOTIVATION: Bus often single-master — parallel seq starts need explicit arbitration.
WHEN: Default for single-driver agent; SEQ_ARB_RANDOM for stress interleaving.
PITFALL: Parallel start without understanding arbitration — starvation surprise.Q: Sequence library pattern — why uvm_sequence_library?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Sequence library?
A:
MECHANISM: Registered seq types + selection mode — regression picks random legal scenario.
MOTIVATION: VIP publishes legal protocol scenarios — integrator does not rewrite.
WHEN: Reusable VIP with 10+ scenario sequences.
PITFALL: Library includes illegal seq — breaks integrator trust.systemverilog
class axi_seq_lib extends uvm_sequence_library #(axi_txn);
`uvm_object_utils(axi_seq_lib)
`uvm_sequence_library_utils(axi_seq_lib)
function new(string name = "");
super.new(name);
init_sequence_library();
add_sequence(axi_write_seq::get_type());
add_sequence(axi_read_seq::get_type());
selection_mode = UVM_SEQ_LIB_RAND;
endfunction
endclassKey takeaways
Virtual seq: declare p_sequencer, start leaf seqs on handles.
Arbitration mode matters for parallel seq.start — name STRICT_FIFO.
Sequence library publishes legal scenarios — VIP integration pattern.
Common pitfalls
Virtual sequencer is not a driver — no get_next_item on v_sqr.
Sequence without raise_objection when test does not hold one — zero-time end.