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Course contents

  • Start Here4
  • UVM Foundations14
  • UVM Phases & Simulation Lifecycle26
  • Factory & Configuration15
  • Transaction-Level Modeling (TLM)13
  • UVM Sequences & Stimulus21
    • Sequence Items and the Driver Handshake
    • Sequence Mechanics: Lifecycle, Sequencer, Responses and Control
      • Sequence Lifecycle and Hooks: What start() Does, Step by Step
      • Inside the Sequencer: Arbitration, Priority and Relevance
      • Responses and Pipelined Drivers
      • Stopping Sequences and Reset
      • Sequences and Objections: Who Keeps the Phase Open
      • The uvm_do Macro Family: What It Expands To
    • Virtual Sequences and Coordination
  • UVM Agents & Protocol VIP21
  • Environment & Test Classes11
  • Checking & Coverage in UVM21
  • UVM Register Abstraction Layer (RAL)22
  • Advanced UVM in Practice13
  • Debug & Regression10
  • Coding Practice47
  • Verification in Industry Practice10
  • Senior Prep: Architecture, Leadership and Interviews32
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‹UVM Sequences & Stimulus
  1. Topics
  2. UVM Verification
  3. UVM Sequences & Stimulus
  4. Sequence Mechanics: Lifecycle, Sequencer, Responses and Control

Part 5 · Sequences · Intermediate

Sequence Mechanics: Lifecycle, Sequencer, Responses and Control

What happens inside seq.start(), how the sequencer arbitrates, how responses travel back, how to stop sequences cleanly around a reset, who owns objections, and what the uvm_do macros hide.

  • 6topics
  • 6lessons
On this page

    The driver handshake is four calls. Behind them sits a good deal of machinery: a lifecycle that start() walks through, an arbitration queue in the sequencer, a response queue in every sequence, and a set of ways to stop all of it. Senior interviews live here, because this is where real benches break: the high-priority sequence that waits anyway, the response queue that silently overflows, the reset that leaves the driver holding a stale item.

    What you will be able to do

    • List what seq.start(sqr, parent, priority, call_pre_post) does, in order, and say when pre_body and post_body are skipped.

    • Explain how the sequencer picks the next sequence in each arbitration mode, and write a custom arbitration function.

    • Return responses from in-order and pipelined drivers without overflowing the response queue, and match them by transaction ID.

    • Stop sequences around a reset without fatals or zombies, and choose who owns the objection.

    • Read a uvm_do macro and write the explicit code it stands for.

    Learning path: lifecycle and hooks, inside the sequencer, responses, stopping and reset, objections; the uvm_do lesson branches from the lifecycle.
    Start with the lifecycle: every later lesson refers to its steps. The macro lesson can be read any time after it.

    The lessons

    Lesson

    What you learn

    Sequence lifecycle and hooks

    The steps of start(), pre_start to post_start, pre_do / mid_do / post_do, call_pre_post, and the sequence states.

    Inside the sequencer

    The arbitration queue, grants, priorities, the six arbitration modes, user_priority_arbitration and is_relevant.

    Responses and pipelined drivers

    The response queue and its depth of 8, item_done(rsp) versus put_response, set_id_info, get_response by ID, response handlers, and an out-of-order driver.

    Stopping sequences and reset

    kill(), stop_sequences(), guarded disable fork, and a reset-aware driver that still calls item_done.

    Sequences and objections

    starting_phase and its replacements, automatic phase objections, default sequences, and why the bench keeps objections in the test.

    The uvm_do macro family

    What each macro expands to, the IEEE 1800.2 forms, and why many teams ban them.

    Several of these lessons show logs from a small lab bench, seq_lab_tb.sv: one agent with a sequencer and a few driver variants, run with Verilator and the same IEEE 1800.2 UVM library as the DMA bench. The DMA bench itself has one driver per interface, and these mechanisms need several.

    Interview

    A favourite senior question: "Your interrupt sequence has priority 500 and still waits behind the polling sequence. Why?" The default arbitration mode, UVM_SEQ_ARB_FIFO, ignores priority. Priority counts only in the WEIGHTED and STRICT modes, and the STRICT modes can starve low-priority traffic. Inside the sequencer shows all six modes on one bench.

    Related topics

    • Up: UVM Sequences & Stimulus

    • Previous topic: Sequence items and the driver handshake

    • Related topic: Virtual sequences

    PreviousNext: Sequence Lifecycle and Hooks: What start() Does, Step by Step

    Up next

    Up nextSequence Lifecycle and Hooks: What start() Does, Step by Step

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    See also

    • Sequence Items and the Driver Handshake
    • Virtual Sequences and Coordination